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No need to alocate more memory than used
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@ -1143,7 +1143,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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module->memories[memory->name] = memory;
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int number_of_bits = net->Size();
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number_of_bits = 1 << ceil_log2(number_of_bits);
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int bits_in_word = number_of_bits;
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FOREACH_PORTREF_OF_NET(net, si, pr) {
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if (pr->GetInst()->Type() == OPER_READ_PORT) {
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