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verific: allow memories to be inferred in loops

This commit is contained in:
N. Engelhardt 2022-04-15 15:10:48 +02:00
parent c1646a00ac
commit 57bc29c64a
1 changed files with 1 additions and 0 deletions
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frontends/verific/verific.cc
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@ -2548,6 +2548,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);