Commit Graph

14052 Commits

Author SHA1 Message Date
Eddie Hung 3065d4092e Fine tune #1699 tests 2020-02-13 15:14:58 -08:00
Eddie Hung 3d2a2e8799 iopadmap: fixes as suggested by @mwkmwkmwk 2020-02-13 14:57:06 -08:00
Eddie Hung 6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung 7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
Eddie Hung f5cc8cfa79 write_xaiger: default value for abc9_init 2020-02-13 12:37:17 -08:00
Eddie Hung f7c0dbecee abc9: fix abc9_arrival for flops 2020-02-13 12:34:09 -08:00
Eddie Hung 00d41905df abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
Eddie Hung ebb11bcea4 iopadmap: move \init attributes from outpad output to its input 2020-02-13 12:05:14 -08:00
N. Engelhardt c2467fdd55 make rpc frontend unix socket test less fragile 2020-02-13 20:52:22 +01:00
Claire Wolf cb7bc6a12f
Merge pull request #1694 from rqou/json_compat_fix
json: Change compat mode to directly emit ints <= 32 bits
2020-02-13 18:30:22 +01:00
Miodrag Milanovic 0ba2a2b1fa Add new logger pass 2020-02-13 13:35:29 +01:00
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing
Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Eddie Hung c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master
$readmem[hb] file inclusion is now relative to the Verilog file
2020-02-10 08:31:01 -08:00
N. Engelhardt 224dc033aa
Merge pull request #1669 from thasti/pyosys-attrs
Make RTLIL attributes accessible via pyosys
2020-02-10 12:38:28 +01:00
whitequark 7cc9d487ff
Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset
manual: explain RTLIL::Wire::{upto,offset}
2020-02-09 20:29:16 +00:00
whitequark 161eba253f manual: explain RTLIL::Wire::{upto,offset}. 2020-02-09 14:54:07 +00:00
R. Ou 20ce4118da json: Change compat mode to directly emit ints <= 32 bits
This increases compatibility with certain older parsers in some cases
that worked before commit 15fae357 but do not work with the current
compat-int mode
2020-02-09 01:01:18 -08:00
Eddie Hung 2e8d6ec0b0 Remove unnecessary comma 2020-02-07 12:45:07 -08:00
Eddie Hung be8bc63f84
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
Fix shiftx2mux, fix yosys-tests
2020-02-07 12:32:08 -08:00
Eddie Hung affae35847 techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
Eddie Hung e6bb7b0782 Fix misc.abc9.abc9_abc9_luts 2020-02-07 08:27:45 -08:00
Marcin Kościelnicki 89adef352f xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki d48950d92d xilinx: Initial support for LUT4 devices.
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
2020-02-07 09:03:22 +01:00
Eddie Hung 1f54b0008f
Merge pull request #1685 from dh73/gowin
Removing cells_sim from GoWin bram techmap
2020-02-06 20:59:21 -08:00
whitequark 6f67dd8df5
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
2020-02-07 02:54:04 +00:00
whitequark c34d7b13f4 ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
  reg [`WIDTH:0] mem [0:`DEPTH];
  integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.

After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.

As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
Marcin Kościelnicki 30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki 95c46ccc55 xilinx: Add support for Spartan 3A DSP block RAMs.
Part of #1550
2020-02-07 01:00:29 +01:00
Eddie Hung 1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
Fix/cleanup +/xilinx/arith_map.v
2020-02-06 13:51:23 -08:00
Diego H 87883f6d88 Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
Eddie Hung d625e399cb Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk 2020-02-06 11:25:07 -08:00
Eddie Hung 5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
Marcin Kościelnicki 8f559b070a edif: more resilience to mismatched port connection sizes.
Fixes #1653.
2020-02-06 18:45:03 +01:00
whitequark 081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark e95a8ba763 write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
whitequark 3f4460a186 ice40: match memory inference attribute values case insensitive.
LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark 60f047f136 memory_bram: add `attr_icase` option.
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
2020-02-06 14:58:20 +00:00
whitequark fc28bf55aa ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
whitequark 29d130dee9 ice40: remove impossible test.
iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo 9da5936c05 Added 'set -e' into tests/memfile/run-test.sh
Also added two checks for situations where the execution must fail.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:45:40 -03:00
Rodrigo Alejandro Melo da485dc007 Modified $readmem[hb] to use '\' or '/' according the OS
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
Eddie Hung d44848328b
Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 20:21:40 -08:00
Eddie Hung 0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
Eddie Hung fc33287bc1 verilog: instead of modifying localparam size, extend init constant expr 2020-02-05 17:19:42 -08:00
Eddie Hung 4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung 505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung 6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
techmap LSB-first for compatible $shift/$shiftx cells
2020-02-05 14:55:57 -08:00