Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Stefan Biereigel
90c78f1f85
add testcase for #1614
2020-02-03 21:29:54 +01:00
Stefan Biereigel
b844b078db
correct wire declaration grammar for #1614
2020-02-03 21:29:40 +01:00
Stefan Biereigel
3d13b10859
remove namespace mention from inheritance information
2020-02-03 20:54:32 +01:00
Stefan Biereigel
362e3aa40f
expose polymorphism through python wrappers
2020-02-03 20:21:02 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master
2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
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As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
David Shah
7033503cd9
Merge pull request #1516 from YosysHQ/dave/dotstar
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sv: Add support for wildcard port connections (.*)
2020-02-02 18:12:28 +00:00
David Shah
0488492ad2
Update CHANGELOG and README
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:13:13 +00:00
David Shah
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
ebe1d7d5ab
sv: More tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
a210675d71
sv: Add tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7
Removed 'synth' into tests/memfile/run-test.sh
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46
Added content1.dat into tests/memfile
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Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
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synth_xilinx: add -dsp-multonly
2020-02-02 14:53:32 +00:00
Marcin Kościelnicki
b44d0e041f
xilinx: use RAM32M/RAM64M for memories with two read ports
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This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
2020-02-02 14:34:21 +01:00
Rodrigo Alejandro Melo
2774aae0f2
Removed a line jump into the CHANGELOG
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 22:56:01 -03:00
Rodrigo Alejandro Melo
eaaba6e091
Added tests/memfile to 'make test' with an extra testcase
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c
Added a test for the Memory Content File inclusion using $readmemb
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:41:10 -03:00
Rodrigo Alejandro Melo
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
David Shah
65716c9982
xilinx_dsp: Add multonly scratchpad var to bypass
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-01 15:30:43 +00:00
Marcin Kościelnicki
00fba62711
json: remove the 32-bit parameter special case
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Before, the rules for encoding parameters in JSON were as follows:
- if the parameter is not a string:
- if it is exactly 32 bits long and there are no z or x bits, emit it
as an int
- otherwise, emit it as a string made of 0/1/x/z characters
- if the parameter is a string:
- if it contains only 0/1/x/z characters, append a space at the end
to distinguish it from a non-string
- otherwise, emit it directly
However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values. Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
2020-02-01 16:16:26 +01:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Rodrigo Alejandro Melo
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
Eddie Hung
a1c840ca5d
Merge pull request #1668 from gsomlo/gls-abc9-external
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abc9: Fix regression breaking support for use of ABCEXTERNAL
2020-01-31 09:34:13 +00:00
Stefan Biereigel
3c9371589d
add inheritance for pywrap generators
2020-01-30 21:26:37 +01:00
Gabriel Somlo
8106c3d31b
abc9: restore ability to use ABCEXTERNAL
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-30 15:12:43 -05:00
Claire Wolf
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand
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Add Verific support for OPER_REDUCE_NAND
2020-01-30 19:55:53 +01:00
Claire Wolf
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help
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`verific` pass to print help message when command syntax error
2020-01-30 18:05:16 +01:00
Claire Wolf
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
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verific: unflatten struct ports
2020-01-30 18:03:35 +01:00
Claire Wolf
23c44afaed
Add Verific support for OPER_REDUCE_NAND
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
Xiretza
90404e1969
Improve ABC repository management in Makefile
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`rev-parse --short` output may have a different abbreviated hash length than
ABCREV, so a simple string comparison always fails, even if the correct
commit is checked out. Pass both commits through rev-parse and then
compare the full hashes instead.
Add an `echo-abc-rev` target so that packaging scripts can set ABCPULL=0 and
handle all the git nastiness themselves.
2020-01-29 19:10:54 +01:00
Xiretza
2a746234fe
Clean up 'install' Makefile target
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- libyosys.so is now only installed to LIBDIR instead of LIBDIR, BINDIR
and PYTHON_DESTDIR
- replace mkdir/cp for single files with `install`
2020-01-29 19:10:54 +01:00
Claire Wolf
1679682fa3
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
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Also some minor fixes to the original PR.
2020-01-29 17:01:24 +01:00
Claire Wolf
4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
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opt_reduce: Call check() per run rather than per optimised cell
2020-01-29 15:27:11 +01:00
Claire Wolf
bc325468e7
Merge pull request #1665 from YosysHQ/clifford/edifkeep
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Preserve wires with keep attribute in EDIF back-end
2020-01-29 15:25:56 +01:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
N. Engelhardt
177a7cb23e
Merge pull request #1510 from pumbor/master
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handle anonymous unions to fix #1080
2020-01-29 15:21:28 +01:00
Claire Wolf
50d70288d0
Preserve wires with keep attribute in EDIF back-end
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-29 14:07:11 +01:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix
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Fix for non-deterministic test
2020-01-29 11:18:06 +01:00