mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
Fix shiftx2mux, fix yosys-tests
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@ -471,7 +471,7 @@ struct Abc9ExePass : public Pass {
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// handle -lut / -luts args
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if (!lut_arg.empty()) {
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string arg = lut_arg;
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if (arg.find_first_not_of("0123456789:") == std::string::npos) {
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if (arg.find_first_not_of("0123456789:,") == std::string::npos) {
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size_t pos = arg.find_first_of(':');
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int lut_mode = 0, lut_mode2 = 0;
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if (pos != string::npos) {
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@ -149,16 +149,14 @@ module _90_shift_shiftx (A, B, Y);
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_TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
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// Halve the size of $shift/$shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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localparam len = 2**(B_WIDTH-1);
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localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
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wire [len-1:0] T, F, AA;
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wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A};
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localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
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localparam len = Y_WIDTH2 * ((entries+1)/2);
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wire [len-1:0] AA;
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wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A};
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genvar i;
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for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
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assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
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assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2];
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assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
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end
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for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
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assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
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wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
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if (_TECHMAP_CELLTYPE_ == "$shift")
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$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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