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caravel
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493 Commits 140 Branches 61 Tags 15 GiB
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76 Commits

Author SHA1 Message Date
manarabdelaty 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets 2021-11-19 15:50:36 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty 098b4befb2 Add gds view for chip_io 2021-11-15 23:02:01 +02:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 10cf11fbf5 Add gds/lef views for simple_por 2021-11-15 18:08:22 +02:00
manarabdelaty 6203460f57 [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-08 13:35:16 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the 
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
 2021-11-06 13:28:26 -04:00
Tim Edwards 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming 
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
 2021-11-06 12:59:49 -04:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00
Tim Edwards a67cbcb01c Added back a couple more files related to the user ID programming block. 2021-10-26 10:40:55 -04:00