riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
775 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

96 Commits

Author SHA1 Message Date
tangxifan 1eac22feba [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration 2020-12-18 20:18:02 -07:00
tangxifan 8a31edb40e [Testbench] Remove compressed testbench file 2020-12-18 19:52:52 -07:00
tangxifan 03316d6e65 [Testbench] Remove signal initialization which is not neccessary for caravel tests 2020-12-18 19:51:54 -07:00
tangxifan e17d51aa9f [Testbench] Bug fix in using power pins 2020-12-18 17:49:16 -07:00
tangxifan f028437fef [Testbench] Update SCFF test to be compatible with simulation with power pins 2020-12-18 16:24:56 -07:00
tangxifan 9e60f62299 [Testbench] Critical bug fix on the caravel testbench for and2_latch benchmark 2020-12-18 16:23:50 -07:00
tangxifan 7b2632a872 [Testbench] Add power pin support to scff testbench 2020-12-18 15:55:05 -07:00
tangxifan 2b0294e40a [Testbench] Recover from LFS 2020-12-18 15:39:00 -07:00
tangxifan 7ea8f77038 [Testbench] Add include netlist for caravel testbench 2020-12-17 20:20:39 -07:00
tangxifan 187364ebc3 [Testbench] Add Caravel testbench for and2_testbench 2020-12-17 20:19:12 -07:00
tangxifan d6b435018c [Testbench] Rename top modules of Caravel testbenches to be compatible with scripted verification flow 2020-12-17 10:45:33 -07:00
tangxifan 46bd96f8e9 [Testbench] Add carevel testbench for ccff test 2020-12-17 10:45:06 -07:00
tangxifan d019166190 [Testbench] Bug fix in Caravel ccff testbench 2020-12-17 10:36:25 -07:00
tangxifan 2d8b4b59db [Testbench] Add ccff_test for caravel 2020-12-16 20:25:21 -07:00
tangxifan 9a23f0b15e [Testbench] Bug fix 2020-12-16 18:56:11 -07:00
tangxifan 5ffdce9ce0 [Testbench] Caravel SCFF testbench is working but see problems in verification 2020-12-16 15:22:22 -07:00
tangxifan f5d78fc0fa [Testbench] Start building caravel testbench 2020-12-16 14:53:52 -07:00
tangxifan e24d643cbd [Testbench] Move Caravel testbenches to a path that can be scripted to run 2020-12-16 13:40:20 -07:00
tangxifan b5fa0733a2 [Testbench] Start build caravel scff test 2020-12-16 11:43:02 -07:00
tangxifan 80d79a6eb1 [Testbench] Add testbenches for RTL and Gate-level netlists of Caravel 2020-12-15 16:13:34 -07:00
tangxifan 501c2799ed [Testbench] Rename testbench to be consistent with post-PnR netlist path change 2020-12-14 20:27:22 -07:00
tangxifan e78b234e00 [Testbench] Bug fix for wrapper testbench include netlist 2020-12-14 13:30:01 -07:00
tangxifan 68c1e17a96 [Testbench] Add more testbenches for CHD post-pnr verification 2020-12-14 13:26:04 -07:00
tangxifan 7c0dc4c871 [Testbench] Restore post-Pnr testbenches for CHD version 2020-12-14 13:17:37 -07:00
tangxifan 1e490c1714 [HDL] Add digital I/O self testing testbench 2020-12-11 16:11:12 -07:00
tangxifan d9e965cf3b [Testbench] Add post-PnR testbenches for SOFA-CHD 2020-12-09 14:55:27 -07:00
tangxifan 73622b1df5 [TESTBENCH] Add more cells that are used by post-PNR CHD FPGA 2020-12-09 12:12:14 -07:00
tangxifan ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA 2020-12-08 15:35:38 -07:00
tangxifan 51167f871e [Testbench] Patch ccff test 2020-12-02 20:07:36 -07:00
tangxifan 7b637e6676 [Testbench] Bug fix in post PnR testbench templates 2020-12-02 17:50:49 -07:00
tangxifan 6814b3bb60 [Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants 2020-12-02 15:22:19 -07:00
tangxifan 20cba3f558 [Testbench] Add testbench for post-PnR verification for FPGA with reset 2020-12-02 13:43:06 -07:00
tangxifan 61163de580 [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset 2020-12-02 12:00:28 -07:00
tangxifan d867dbb1bf [Testbench] Bug fix in calling sub python script 2020-12-01 08:14:43 -07:00
tangxifan 11d4b156b4 [Testbench] Bug fix in finding scripts 2020-11-30 22:41:29 -07:00
tangxifan c676db1fe4 [Testbench] Bug fix in the ccff post-pnr testbench template 2020-11-30 11:18:42 -07:00
tangxifan c638edfc14 [Testbench] Regenerate ccff/scff testbenches for wrapper 2020-11-30 10:33:50 -07:00
tangxifan e63cb7ca89 [Testbench] Rename testbench top module to be compatible with verification scripts 2020-11-30 10:23:30 -07:00
tangxifan c70d5ac4f0 [Testbench] Add ccff test wrapper testbench and include netlist 2020-11-30 09:42:31 -07:00
tangxifan 2b40d5fb4b [HDL] Bug fix 2020-11-30 09:34:26 -07:00
tangxifan fc3eadaf29 [Testbench] Add SCFF test for wrapper 2020-11-29 22:58:48 -07:00
tangxifan 0bf5a400e8 [Testbench] Add include netlists for wrapper testbenches 2020-11-29 22:48:25 -07:00
tangxifan 0ccc18d848 [Testbench] Bug fix in the paths to generate wrapper testbenches 2020-11-29 22:48:01 -07:00
tangxifan 931b93b83d [Testbench] Now wrapper testbench conversion can be batched 2020-11-29 22:38:16 -07:00
tangxifan 12c3e157bf [Testbench] Add a tempo fix on the analog pins 2020-11-29 22:32:36 -07:00
tangxifan 50089e11f9 [Testbench] Bug fix 2020-11-29 22:20:15 -07:00
tangxifan 4b681b88a6 [Testbench] Fix the unconnected wbs_we_i pin 2020-11-29 22:17:10 -07:00
tangxifan 724696a661 [Testbench] Add missing ports in the wrapper 2020-11-29 22:16:04 -07:00
tangxifan 5235424e83 [Testbench] Adapt path for signal init in testbench converter 2020-11-29 21:44:29 -07:00
tangxifan fec19ebc55 [Testbench] Typo fix 2020-11-29 21:19:56 -07:00