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[Testbench] Bug fix

This commit is contained in:
tangxifan 2020-11-29 22:20:15 -07:00
parent 4b681b88a6
commit 50089e11f9
1 changed files with 2 additions and 0 deletions
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2
TESTBENCH/common/post_pnr_wrapper_testbench_converter.py
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@ -236,6 +236,8 @@ with open(args.post_pnr_testbench, "r") as wp:
+ "wire [`MPRJ_IO_PADS-1:0] io_oeb;\n" \
+ "// ---- Analog I/O pins ----\n" \
+ "wire [`MPRJ_IO_PADS-8:0] analog_io;\n"
+ "// ---- User clock pin ----\n" \
+ "wire [0:0] user_clock2;\n"
# Skip all the lines about FPGA instanciation
if (curr_line == "\tfpga_core FPGA_DUT (\n"):