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[Testbench] Adapt path for signal init in testbench converter

This commit is contained in:
tangxifan 2020-11-29 21:44:29 -07:00
parent fec19ebc55
commit 5235424e83
1 changed files with 5 additions and 1 deletions
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6
TESTBENCH/common/post_pnr_wrapper_testbench_converter.py
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@ -197,7 +197,7 @@ with open(args.post_pnr_testbench, "r") as wp:
# If the current line satisfy the following conditions
# It should be modified and outputted to post-PnR Verilog testbenches
# Other lines can be directly copied to post-PnR Verilog testbenches
line2output = curr_line \
line2output = curr_line
#
# Add post_pnr to top-level module name
if (curr_line.startswith("module")):
@ -274,6 +274,10 @@ with open(args.post_pnr_testbench, "r") as wp:
+ "\t\t\t);\n";
# Wire the stimuli according to pin assignment
write_testbench_wrapper_connection(tb_file, pin_data, 25)
# Correct the path in signal initialization
if (re.search(r'\$deposit\(FPGA_DUT', curr_line)):
line2output = re.sub(r'\$deposit\(FPGA_DUT', '$deposit(FPGA_DUT.fpga_core_uut', curr_line)
if (False == skip_current_line):
tb_file.write(line2output)