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SOFA
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814 Commits 16 Branches 1 Tag 1.8 GiB
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93 Commits

Author SHA1 Message Date
Ganesh Gore f5ff147ddb Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
tangxifan a017a2f23c [Script] Add example openfpga shell script for the Sofa+ arch 2021-05-19 13:40:49 -06:00
Andrew Pond 3dcdad3253 updated to use timing annotation file 2021-04-06 08:12:34 -06:00
Andrew Pond 2fc7cf5b71 repo setup script 2021-04-03 12:13:19 -06:00
Andrew Pond 1fc9e0574c Merge branch 'master' into arch_exploration 
Merge master fix into branch
 2021-04-03 11:38:01 -06:00
Andrew Pond 14062a971e fixed vexriscv task template 2021-04-03 11:12:40 -06:00
Andrew Pond 0c7e74299e added Vexriscv task files 2021-04-03 11:04:14 -06:00
tangxifan 220506cd3f [Test] Add task configuration file for bitstream generation flow 2021-04-03 10:38:23 -06:00
tangxifan e9fa1bf243 [Script] Add openfpga shell script for bitstream generation 2021-04-03 10:19:02 -06:00
tangxifan b22584e7a1 [MISC] Bug fixes for wrong paths in task configuration files; typo in arch files 2021-04-01 21:16:08 -06:00
tangxifan 4aea849cf9 [Script] Add design varaibles to task configuration files 2021-04-01 21:06:22 -06:00
tangxifan 7e4595068a [Script] Add design variables to task configuration files 2021-04-01 20:29:30 -06:00
tangxifan bafecc625b [Script] Bug fix 2021-03-31 14:20:37 -06:00
tangxifan 7faf529538 [Script] Bypass jpng benchmark 2021-03-31 13:17:28 -06:00
tangxifan 775881e529 [Script] Bypass cavlc due to yosys synthesis problems 2021-03-31 12:29:24 -06:00
tangxifan 7d8812b844 [Script] Add missing QL synthesis arguments 2021-03-31 11:52:21 -06:00
tangxifan 7643950572 [Script] Fix the mismatched name of Quicklogic's yosys scripts in task configuration files 2021-03-31 10:54:10 -06:00
Andrew Pond c34d20824b added arch exploration files 2021-03-10 22:26:06 -07:00
Lalit Sharma 0cdd94139f using default yosys script instead of custom script for multi_enc_decx2x4 design as custom script generated blif file is causing an assertion in openfpga. This is done temporarily to enable developers to checkin in SOFA, also requested Xifan to review this crash in openfpga. 2021-02-03 01:08:27 -08:00
Lalit Sharma c34c777409 Using custom yosys script for benchmarks run in generate_testbench task 2021-01-20 21:18:38 -08:00
Lalit Sharma 4128f4cd1b Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated 2021-01-07 01:15:41 -08:00
Lalit Sharma 847d0ec8f6 Adding io_reg related simple design 2021-01-06 23:24:34 -08:00
Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys 2021-01-06 23:19:20 -08:00
Tarachand Pagarani 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space 
limitation on github actions.
Disable testcase not fitting on 32x32 device
 2021-01-05 19:44:08 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Ganesh Gore f494c31ca0 [Action] More cleanup while precheck 2020-12-20 17:04:56 -07:00
Ganesh Gore 37bca4684b [BugFix] After Integration with mpw-one-b 2020-12-17 09:29:54 -07:00
Tarachand Pagarani 8d5036f108 commented/corrected failing benchmarks 2020-12-17 05:46:30 -08:00
Tarachand Pagarani c264ee0ddd add more benchmark tests 2020-12-17 02:17:20 -08:00
Tarachand Pagarani cfdaedcdd0 added script with random key generation example 2020-12-17 01:42:19 -08:00
Tarachand Pagarani b556cf452c add tasks for 32x32 configuration 2020-12-17 01:40:19 -08:00
Ganesh Gore 3c174619b0 [Action] Updated action script for local run 2020-12-14 12:08:16 -07:00
Ganesh Gore def270a94b [Actions] Launched checker in correct directory 2020-12-08 21:50:18 -07:00
Ganesh Gore 3ecd96596f [Actions] Merged Caravel with Klayout 2020-12-08 13:33:17 -07:00
Ganesh Gore b0098ed4b9 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-06 21:29:06 -07:00
Ganesh Gore 10cab93799 [Action] Integrated MPW prechecker 2020-12-06 01:41:58 -07:00
tangxifan c015d65a03 [Script] Add task run for custom cell FPGA architectures 2020-12-06 01:40:21 -07:00
tangxifan 696529b43d [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-06 01:39:16 -07:00
tangxifan 2db2b468fe [Script] Try auto number of simulation clock cycles 2020-12-02 19:33:28 -07:00
tangxifan 930f7ec486 [Script] Remove task run for redundant architectures 2020-12-02 17:56:58 -07:00
tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
tangxifan 147dd8d606 [Script] Add task run for custom cell FPGA architectures 2020-12-01 20:22:16 -07:00
tangxifan 0eb1b68bee [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-01 10:17:47 -07:00
tangxifan 6a12cdbad1 [Script] Add task run for the architecture with both reset and soft adders 2020-11-27 18:15:05 -07:00
tangxifan e5a66dd47f [Script] Add task run for softadder architecture 2020-11-27 16:14:14 -07:00
tangxifan 28c8dba87b [Script] Bug fix in task configuration files 2020-11-27 15:05:35 -07:00