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[Script] Add design varaibles to task configuration files

This commit is contained in:
tangxifan 2021-04-01 21:06:22 -06:00
parent 7059c6a014
commit 4aea849cf9
6 changed files with 6 additions and 0 deletions
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1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga