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fabric_verilog_options.cpp
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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fabric_verilog_options.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_api.cpp
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_api.h
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_auxiliary_netlists.cpp
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[core] now default net type wire will not appear. timescale does not show in fabric netlists
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2023-09-06 22:27:51 -07:00 |
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verilog_auxiliary_netlists.h
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[core] now fabric netlist include mock wrapper
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2023-05-26 18:49:57 -07:00 |
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verilog_constants.h
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[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
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2024-03-29 10:57:45 -07:00 |
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verilog_decoders.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_decoders.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_essential_gates.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_essential_gates.h
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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verilog_formal_random_top_testbench.cpp
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[core] code format
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2023-09-17 22:37:48 -07:00 |
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verilog_formal_random_top_testbench.h
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[core] code format
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2023-09-17 22:37:48 -07:00 |
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verilog_grid.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_grid.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_lut.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_lut.h
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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verilog_memory.cpp
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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verilog_memory.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_mock_fpga_wrapper.cpp
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[core] fixed some bugs
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2023-09-18 16:39:07 -07:00 |
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verilog_mock_fpga_wrapper.h
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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verilog_module_writer.cpp
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[core] code format
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2023-09-06 22:29:30 -07:00 |
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verilog_module_writer.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_mux.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_mux.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_port_types.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_preconfig_top_module.cpp
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[core] code format
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2024-03-29 10:58:48 -07:00 |
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verilog_preconfig_top_module.h
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_preconfig_top_module_utils.cpp
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_preconfig_top_module_utils.h
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_routing.cpp
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[core] code format
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2023-10-19 23:05:49 -07:00 |
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verilog_routing.h
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[core] code format
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2023-09-16 18:24:38 -07:00 |
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verilog_shift_register_banks.cpp
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_shift_register_banks.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_simulation_info_writer.cpp
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_simulation_info_writer.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_submodule.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_submodule.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_submodule_utils.cpp
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[core] now default net type wire will not appear. timescale does not show in fabric netlists
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2023-09-06 22:27:51 -07:00 |
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verilog_submodule_utils.h
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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verilog_template_testbench.cpp
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_template_testbench.h
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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verilog_testbench_io_connection.cpp
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[core] add missing files
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2023-11-02 19:01:25 -07:00 |
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verilog_testbench_io_connection.h
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[core] add missing files
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2023-11-02 19:01:25 -07:00 |
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verilog_testbench_options.cpp
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[code] syntax
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2024-03-29 11:03:48 -07:00 |
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verilog_testbench_options.h
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[code] syntax
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2024-03-29 11:03:48 -07:00 |
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verilog_testbench_utils.cpp
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[core] typo
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2024-03-29 12:03:23 -07:00 |
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verilog_testbench_utils.h
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[core] code format
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2024-03-29 10:58:48 -07:00 |
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verilog_tile.cpp
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[core] code format
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2023-09-16 18:24:38 -07:00 |
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verilog_tile.h
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[core] fixed some bugs in verilog writer due to renaming
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2023-09-16 18:13:22 -07:00 |
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verilog_top_module.cpp
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[core] fixed a bug
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2023-09-18 20:43:15 -07:00 |
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verilog_top_module.h
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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verilog_top_testbench.cpp
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[core] add a new option for simulator type to verilog full testbench generator
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2023-12-08 13:07:25 -08:00 |
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verilog_top_testbench.h
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_top_testbench_constants.h
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[core] developing testbench generator for ccff v2
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2023-04-24 11:36:21 +08:00 |
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verilog_top_testbench_memory_bank.cpp
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[core] code format
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2023-12-08 13:41:41 -08:00 |
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verilog_top_testbench_memory_bank.h
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[core] add a new option for simulator type to verilog full testbench generator
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2023-12-08 13:07:25 -08:00 |
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verilog_wire.cpp
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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verilog_wire.h
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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verilog_writer_utils.cpp
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[core] code format
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2023-09-06 22:40:59 -07:00 |
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verilog_writer_utils.h
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[core] code format
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2023-09-06 22:29:30 -07:00 |
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