119 lines
4.9 KiB
C++
119 lines
4.9 KiB
C++
#ifndef VERILOG_API_H
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#define VERILOG_API_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "bitstream_manager.h"
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#include "bus_group.h"
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#include "circuit_library.h"
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#include "config_protocol.h"
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#include "decoder_library.h"
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#include "device_rr_gsb.h"
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#include "fabric_bitstream.h"
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#include "fabric_global_port_info.h"
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#include "fabric_tile.h"
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#include "fabric_verilog_options.h"
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#include "io_location_map.h"
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#include "io_name_map.h"
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#include "memory_bank_shift_register_banks.h"
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#include "module_manager.h"
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#include "module_name_map.h"
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#include "mux_library.h"
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#include "netlist_manager.h"
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#include "pin_constraints.h"
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#include "simulation_setting.h"
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#include "verilog_testbench_options.h"
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#include "vpr_context.h"
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#include "vpr_device_annotation.h"
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#include "vpr_netlist_annotation.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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int fpga_fabric_verilog(
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ModuleManager& module_manager, NetlistManager& netlist_manager,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
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const DecoderLibrary& decoder_lib, const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
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const ModuleNameMap& module_name_map, const FabricVerilogOption& options);
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int fpga_verilog_full_testbench(
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const ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager,
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const FabricBitstream& fabric_bitstream,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const AtomContext& atom_ctx, const PlacementContext& place_ctx,
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const PinConstraints& pin_constraints, const BusGroup& bus_group,
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const std::string& bitstream_file, const IoLocationMap& io_location_map,
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const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
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const FabricGlobalPortInfo& fabric_global_port_info,
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const VprNetlistAnnotation& netlist_annotation,
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const CircuitLibrary& circuit_lib,
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const SimulationSetting& simulation_parameters,
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const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options);
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int fpga_verilog_preconfigured_fabric_wrapper(
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const ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
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const BusGroup& bus_group, const IoLocationMap& io_location_map,
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const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
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const FabricGlobalPortInfo& fabric_global_port_info,
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const VprNetlistAnnotation& netlist_annotation,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
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const VerilogTestbenchOption& options);
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int fpga_verilog_template_testbench(const ModuleManager& module_manager,
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const IoNameMap& io_name_map,
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const ModuleNameMap& module_name_map,
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const VerilogTestbenchOption& options);
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int fpga_verilog_testbench_io_connection(
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const ModuleManager& module_manager, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
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const BusGroup& bus_group, const IoLocationMap& io_location_map,
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const ModuleNameMap& module_name_map,
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const FabricGlobalPortInfo& fabric_global_port_info,
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const VprNetlistAnnotation& netlist_annotation,
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const VerilogTestbenchOption& options);
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int fpga_verilog_mock_fpga_wrapper(
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const ModuleManager& module_manager, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
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const BusGroup& bus_group, const IoLocationMap& io_location_map,
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const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
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const FabricGlobalPortInfo& fabric_global_port_info,
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const VprNetlistAnnotation& netlist_annotation,
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const VerilogTestbenchOption& options);
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int fpga_verilog_preconfigured_testbench(
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const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
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const AtomContext& atom_ctx, const PinConstraints& pin_constraints,
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const BusGroup& bus_group,
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const FabricGlobalPortInfo& fabric_global_port_info,
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const VprNetlistAnnotation& netlist_annotation,
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const SimulationSetting& simulation_setting,
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const VerilogTestbenchOption& options);
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int fpga_verilog_simulation_task_info(
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const ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
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const SimulationSetting& simulation_setting,
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const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options);
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} /* end namespace openfpga */
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#endif
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