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fabric_verilog_options.cpp
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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fabric_verilog_options.h
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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simulation_info_writer.cpp
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now generating simulation ini file will try to create directory first
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2020-04-15 20:53:37 -06:00 |
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simulation_info_writer.h
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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verilog_api.cpp
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improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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verilog_api.h
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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verilog_auxiliary_netlists.cpp
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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verilog_auxiliary_netlists.h
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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verilog_constants.h
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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verilog_decoders.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_decoders.h
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_essential_gates.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_essential_gates.h
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_formal_random_top_testbench.cpp
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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verilog_formal_random_top_testbench.h
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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verilog_grid.cpp
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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verilog_grid.h
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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verilog_lut.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_lut.h
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_memory.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_memory.h
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_module_writer.cpp
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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verilog_module_writer.h
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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verilog_mux.cpp
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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verilog_mux.h
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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verilog_port_types.h
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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verilog_preconfig_top_module.cpp
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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verilog_preconfig_top_module.h
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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verilog_routing.cpp
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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verilog_routing.h
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routing module Verilog writer is online
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2020-02-16 14:47:54 -07:00 |
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verilog_submodule.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_submodule.h
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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verilog_submodule_utils.cpp
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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verilog_submodule_utils.h
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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verilog_testbench_options.cpp
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add warning to force formal_verification_top_netlist enabled
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2020-02-27 13:28:21 -07:00 |
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verilog_testbench_options.h
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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verilog_testbench_utils.cpp
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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verilog_testbench_utils.h
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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verilog_top_module.cpp
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |
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verilog_top_module.h
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |
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verilog_top_testbench.cpp
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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verilog_top_testbench.h
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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verilog_wire.cpp
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_wire.h
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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verilog_writer_utils.cpp
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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verilog_writer_utils.h
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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