tangxifan 1a8968cb37 now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML		2020-04-20 21:12:51 -06:00
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annotation	critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results	2020-04-18 21:04:46 -06:00
base	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
fabric	critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA	2020-04-13 12:58:44 -06:00
fpga_bitstream	relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics	2020-03-27 19:07:34 -06:00
fpga_sdc	now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML	2020-04-20 21:12:51 -06:00
fpga_verilog	now generating simulation ini file will try to create directory first	2020-04-15 20:53:37 -06:00
mux_lib	spot a bug in assigning rr_switch in tileable routing	2020-03-20 16:53:43 -06:00
repack	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	fix memory leakage in openfpga title	2020-04-07 16:14:41 -06:00