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Final1.1

v0.1-alpha

v0.2-alpha

v0.3-alpha

v1.1.0

v1.1.525

v1.1.541

v1.2.0

Mono Color

• 96783f31c3 Updated Patch Count github-actions[bot] 2024-08-06 19:55:50 +0000
• f456fef23d
  Merge pull request #1778 from lnis-uofu/dependabot/submodules/yosys-d2b5788 tangxifan 2024-08-06 12:55:27 -0700
• 5a70503317
  Bump yosys from `c788484` to `d2b5788` dependabot[bot] 2024-08-06 06:31:32 +0000
• 72a90a4d8f add preload function Lin 2024-08-05 19:42:21 -0700
• c726744154 add sb unique modules Lin 2024-08-05 02:23:47 -0700
• 5ac19ea628 read unique blocks io Lin 2024-08-04 20:51:27 -0700
• 10b5dc5e6b
  Merge pull request #1777 from lnis-uofu/patch_update tangxifan 2024-08-03 15:08:13 -0700
• a0cb78f6ae Updated Patch Count github-actions[bot] 2024-08-03 22:04:50 +0000
• a7920b16a9
  Merge pull request #1776 from lnis-uofu/xt_doc tangxifan 2024-08-03 15:04:09 -0700
• c11a2c7381 [doc] format to resolve latexpdf build errors; now local build passes tangxifan 2024-08-03 15:03:14 -0700
• 328c3873cc
  Merge pull request #1775 from lnis-uofu/patch_update tangxifan 2024-08-03 14:58:52 -0700
• 92b0df57a9 Updated Patch Count github-actions[bot] 2024-08-03 21:35:23 +0000
• d6f26863e8
  Merge pull request #1774 from lnis-uofu/xt_doc tangxifan 2024-08-03 14:35:05 -0700
• c85bf97c06
  Update .readthedocs.yml tangxifan 2024-08-03 00:26:24 -0700
• 23f43459bd
  Merge pull request #1773 from lnis-uofu/patch_update tangxifan 2024-08-02 21:23:35 -0700
• 94c6b6322a Updated Patch Count github-actions[bot] 2024-08-03 04:00:29 +0000
• 0edd5529c3
  Merge pull request #1772 from lnis-uofu/xt_fkey tangxifan 2024-08-02 21:00:06 -0700
• 8a07564d80
  Merge branch 'master' into xt_fkey tangxifan 2024-08-02 19:11:49 -0700
• 57adf97fd4 [test] fixed some bugs in clock arch tangxifan 2024-08-02 18:34:59 -0700
• 2e6b311d04 [core] add more details to debug messages tangxifan 2024-08-02 18:33:43 -0700
• 91c4336a4a [test] add a new testcase to validate 3-layer clock architecture tangxifan 2024-08-02 18:18:49 -0700
• eeaa3373c6 [core] code format tangxifan 2024-08-02 17:48:47 -0700
• 82cf7bbb8c [core] Add verbose mode on find_node() for clock rr graph tangxifan 2024-08-02 17:47:41 -0700
• 84c2b27c7b [test] add a new test to validate that pb_pin fix is now compatible with perimeter cb tangxifan 2024-08-02 17:24:44 -0700
• ae1100ceba [core] cleanup debug message tangxifan 2024-08-02 17:05:59 -0700
• 1ec5847d5a [core] typo tangxifan 2024-08-02 14:27:43 -0700
• f44c45bdd3 [core] code format tangxifan 2024-08-02 14:23:35 -0700
• 6a7929973d
  Merge pull request #1771 from lnis-uofu/patch_update tangxifan 2024-08-02 14:21:55 -0700
• 2986a5c5ee Updated Patch Count github-actions[bot] 2024-08-02 21:21:28 +0000
• f7e30b9974 [core] fixed a bug where pb pin fixup does not support perimeter cb tangxifan 2024-08-02 14:21:22 -0700
• 39f6cd13d9
  Merge pull request #1770 from lnis-uofu/xt_fkey tangxifan 2024-08-02 14:21:08 -0700
• ad38b52a23 [lib] code format tangxifan 2024-08-02 12:41:00 -0700
• 1a13c5f815 [lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys tangxifan 2024-08-02 12:31:55 -0700
• 7f426d5939 add commands Lin 2024-08-02 03:10:10 -0700
• 48a386c9b6 add read and write uniqueblocks commands Lin 2024-08-02 01:43:01 -0700
• c04c8c7ac2
  Bump vtr-verilog-to-routing from `9eef18c` to `42829ed` dependabot[bot] 2024-08-02 06:25:10 +0000
• d7a83ecbec
  Merge pull request #1768 from lnis-uofu/patch_update tangxifan 2024-07-31 14:06:12 -0700
• 48a8184072
  Merge branch 'master' into dependabot/submodules/vtr-verilog-to-routing-51bd666 tangxifan 2024-07-31 14:06:03 -0700
• c05b06ef61 Updated Patch Count github-actions[bot] 2024-07-31 21:05:29 +0000
• 6ea1feb445
  Merge pull request #1756 from chungshien/openfpga-overwrite-bits tangxifan 2024-07-31 14:05:04 -0700
• b3c8c529d5
  Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits chungshien 2024-07-31 12:25:37 -0700
• 766df0a1b5 Improve Port Parser chungshien-chai 2024-07-31 12:19:30 -0700
• 0144a6c8fa
  Bump vtr-verilog-to-routing from `9eef18c` to `51bd666` dependabot[bot] 2024-07-31 06:41:16 +0000
• 4defb9e514
  Merge pull request #1766 from lnis-uofu/patch_update tangxifan 2024-07-30 21:00:01 -0700
• c88774bf5e Updated Patch Count github-actions[bot] 2024-07-31 03:59:21 +0000
• 6a88e7befb
  Merge pull request #1765 from lnis-uofu/xt_clkntwk2 tangxifan 2024-07-30 20:59:02 -0700
• d6db51f29e [core] code format tangxifan 2024-07-30 19:09:31 -0700
• ef6b6f8e40 [core] remove warnings tangxifan 2024-07-30 18:50:49 -0700
• ae95357991 [core] code format tangxifan 2024-07-30 15:40:41 -0700
• a2c3af60d7 [core] fixed a bug where unique cb module is not considered as entry point tangxifan 2024-07-30 15:39:44 -0700
• 3181f2d5a3 [test] add a new test to validate multiple entry points for a clock network tangxifan 2024-07-30 14:17:14 -0700
• 687f03fd77 [test] add a new test to validate clock network on module named by index tangxifan 2024-07-30 14:06:53 -0700
• 853883cd36 [core] code format tangxifan 2024-07-30 12:56:03 -0700
• f9f9aab7d9 [test] typo tangxifan 2024-07-30 12:50:14 -0700
• ad275fba44 [test] add a new test to validate clock network entry point on a y-direction cb tangxifan 2024-07-30 12:48:35 -0700
• b6b038a73d [test] add a new arch to test y- entry point of clock network tangxifan 2024-07-30 12:40:41 -0700
• 234eee19ae [core] revert tangxifan 2024-07-30 12:29:32 -0700
• 6a5e0e2f49 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2 tangxifan 2024-07-30 12:23:31 -0700
• 0aa9c4c6af
  Merge pull request #1764 from lnis-uofu/patch_update tangxifan 2024-07-30 11:42:29 -0700
• a2906c4c94 Updated Patch Count github-actions[bot] 2024-07-30 18:42:13 +0000
• 9ef31e6aec
  Merge pull request #1762 from lnis-uofu/dependabot/submodules/yosys-c788484 tangxifan 2024-07-30 11:41:55 -0700
• 44f63cb897
  Merge pull request #1763 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-9eef18c tangxifan 2024-07-30 11:41:42 -0700
• 4d479f9d8c
  Bump vtr-verilog-to-routing from `ddc3ac4` to `9eef18c` dependabot[bot] 2024-07-30 07:00:11 +0000
• 9e59a1fa4a
  Bump yosys from `960bca0` to `c788484` dependabot[bot] 2024-07-30 07:00:09 +0000
• ca48841ae3 Pass in the OpenFPGA root dir chungshien-chai 2024-07-29 11:04:03 -0700
• 5f45d13bfd
  Merge branch 'master' into openfpga-overwrite-bits tangxifan 2024-07-29 16:22:02 +0800
• 61d4114b64 Updated Patch Count github-actions[bot] 2024-07-29 08:07:16 +0000
• 7f9dffec89
  Merge pull request #1760 from lnis-uofu/dependabot/submodules/yosys-960bca0 tangxifan 2024-07-29 16:06:55 +0800
• 3c547f2131
  Bump yosys from `610d27d` to `960bca0` dependabot[bot] 2024-07-29 06:09:43 +0000
• aa3608428e
  Merge 57cb496314 into 4a07a32902 chungshien 2024-07-28 19:53:29 -0700
• 3e3f089823 Get the filepath using definition under [OpenFPGA_SHELL] chungshien-chai 2024-07-28 19:24:48 -0700
• 0d9f1a3c6b Forward searching the config bit + some minor refactor chungshien-chai 2024-07-28 19:12:34 -0700
• 9882394c8b Use archfpga_throw chungshien-chai 2024-07-28 02:53:18 -0700
• ae5b9a3f72
  Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits chungshien 2024-07-28 02:52:18 -0700
• 22d7df5ffb Update doc chungshien-chai 2024-07-28 02:40:24 -0700
• 2a3d69aded Update code based on feedback chungshien-chai 2024-07-28 02:37:15 -0700
• 4a07a32902
  Merge pull request #1759 from lnis-uofu/patch_update tangxifan 2024-07-28 17:04:48 +0800
• ec4be3595b Updated Patch Count github-actions[bot] 2024-07-28 09:04:21 +0000
• f5051398b5
  Merge pull request #1758 from lnis-uofu/dependabot/submodules/yosys-610d27d tangxifan 2024-07-28 17:04:04 +0800
• cbe9a46f95 Format and update doc chungshien-chai 2024-07-28 00:02:20 -0700
• 933155b08f Update test flow chungshien-chai 2024-07-27 23:52:54 -0700
• 0ff0c3445e Update doc chungshien-chai 2024-07-26 13:43:31 -0700
• fbe5ae6bd3 Update test chungshien-chai 2024-07-26 02:18:08 -0700
• 9641aaf6c4 Update test chungshien-chai 2024-07-26 02:17:25 -0700
• 6974e1b7e7
  Merge branch 'master' into openfpga-overwrite-bits chungshien 2024-07-26 01:37:57 -0700
• e60777d23e Use Bitstream Setting XML chungshien-chai 2024-07-26 01:36:49 -0700
• 67bc1b569b
  Bump yosys from `118b282` to `610d27d` dependabot[bot] 2024-07-26 06:52:25 +0000
• aed082817e
  Merge pull request #1757 from lnis-uofu/patch_update tangxifan 2024-07-26 10:28:21 +0800
• b635d17358 Updated Patch Count github-actions[bot] 2024-07-26 02:07:52 +0000
• 4bf4a77861
  Merge pull request #1754 from lnis-uofu/dependabot/submodules/yosys-118b282 tangxifan 2024-07-26 10:07:28 +0800
• 2ef362d53d Init support overwriting bitstream chungshien-chai 2024-07-25 17:40:46 -0700
• f142c73a11
  Merge branch 'lnis-uofu:master' into master chungshien 2024-07-25 12:53:25 -0700
• 542d422911 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2 tangxifan 2024-07-22 21:56:00 +0800
• cd9f533292
  Bump yosys from `28ebefd` to `118b282` dependabot[bot] 2024-07-22 06:13:18 +0000
• 0d82682a73
  Merge pull request #1753 from lnis-uofu/patch_update tangxifan 2024-07-21 11:35:44 +0800
• 9570726ab9 Updated Patch Count github-actions[bot] 2024-07-21 03:13:52 +0000
• ce17197614
  Merge pull request #1751 from lnis-uofu/dependabot/submodules/yosys-28ebefd tangxifan 2024-07-21 11:13:31 +0800
• df0d64ddb4
  Bump yosys from `b08688f` to `28ebefd` dependabot[bot] 2024-07-19 06:34:08 +0000
• 1513ea749b [core] supporting clk spine on the same direction tangxifan 2024-07-16 22:12:51 -0700
• 18d12109fb [core] fixed a critical bug where cb port name using index is not considered on clock network entry tangxifan 2024-07-16 17:42:21 -0700