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Merge pull request #1772 from lnis-uofu/xt_fkey 

[core] fixed a bug where pb pin fixup does not support perimeter cb
This commit is contained in:
tangxifan 2024-08-02 21:00:06 -07:00 committed by GitHub
parent 6a7929973d 8a07564d80
commit 0edd5529c3
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
17 changed files with 257 additions and 49 deletions
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15
libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp
View File

@ -10,7 +10,8 @@ RRClockSpatialLookup::RRClockSpatialLookup() {}
RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree,
const ClockLevelId& lvl,
const ClockTreePinId& pin,
const Direction& direction) const {
const Direction& direction,
const bool& verbose) const {
size_t dir = size_t(direction);
/* Pre-check: the x, y, side and ptc should be non negative numbers!
* Otherwise, return an invalid id */
@ -25,33 +26,33 @@ RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree,
* - Return an invalid id if any out-of-range is detected
*/
if (size_t(dir) >= rr_node_indices_.size()) {
VTR_LOG("Direction out of range");
VTR_LOGV(verbose, "Direction out of range\n");
return RRNodeId::INVALID();
}
if (size_t(x) >= rr_node_indices_[dir].dim_size(0)) {
VTR_LOG("X out of range");
VTR_LOGV(verbose, "X out of range\n");
return RRNodeId::INVALID();
}
if (size_t(y) >= rr_node_indices_[dir].dim_size(1)) {
VTR_LOG("Y out of range");
VTR_LOG("Y out of range\n");
return RRNodeId::INVALID();
}
if (size_t(tree) >= rr_node_indices_[dir][x][y].size()) {
VTR_LOG("Tree id out of range");
VTR_LOGV(verbose, "Tree id out of range\n");
return RRNodeId::INVALID();
}
if (size_t(lvl) == rr_node_indices_[dir][x][y][size_t(tree)].size()) {
VTR_LOG("Level id out of range");
VTR_LOGV(verbose, "Level id out of range\n");
return RRNodeId::INVALID();
}
if (size_t(pin) ==
rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) {
VTR_LOG("Pin id out of range");
VTR_LOGV(verbose, "Pin id out of range\n");
return RRNodeId::INVALID();
}

2
libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h
View File

@ -58,7 +58,7 @@ class RRClockSpatialLookup {
*/
RRNodeId find_node(int x, int y, const ClockTreeId& tree,
const ClockLevelId& lvl, const ClockTreePinId& pin,
const Direction& direction) const;
const Direction& direction, const bool& verbose) const;
/* -- Mutators -- */
public:

30
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -262,7 +262,7 @@ static std::vector<RRNodeId> find_clock_track2track_node(
const RRClockSpatialLookup& clk_rr_lookup, const t_rr_type& chan_type,
const vtr::Point<size_t>& chan_coord, const ClockTreeId& clk_tree,
const ClockLevelId& clk_lvl, const ClockTreePinId& clk_pin,
const Direction& direction) {
const Direction& direction, const bool& verbose) {
std::vector<RRNodeId> des_nodes;
/* Straight connection */
@ -285,7 +285,7 @@ static std::vector<RRNodeId> find_clock_track2track_node(
}
RRNodeId straight_des_node =
clk_rr_lookup.find_node(straight_des_coord.x(), straight_des_coord.y(),
clk_tree, clk_lvl, clk_pin, direction);
clk_tree, clk_lvl, clk_pin, direction, verbose);
if (rr_graph_view.valid_node(straight_des_node)) {
VTR_ASSERT(chan_type == rr_graph_view.node_type(straight_des_node));
des_nodes.push_back(straight_des_node);
@ -344,7 +344,7 @@ static std::vector<RRNodeId> find_clock_track2track_node(
}
RRNodeId left_des_node =
clk_rr_lookup.find_node(left_des_coord.x(), left_des_coord.y(), clk_tree,
next_clk_lvl, clk_pin, left_direction);
next_clk_lvl, clk_pin, left_direction, verbose);
if (rr_graph_view.valid_node(left_des_node)) {
VTR_ASSERT(left_des_chan_type == rr_graph_view.node_type(left_des_node));
des_nodes.push_back(left_des_node);
@ -396,7 +396,7 @@ static std::vector<RRNodeId> find_clock_track2track_node(
}
RRNodeId right_des_node =
clk_rr_lookup.find_node(right_des_coord.x(), right_des_coord.y(), clk_tree,
next_clk_lvl, clk_pin, right_direction);
next_clk_lvl, clk_pin, right_direction, verbose);
if (rr_graph_view.valid_node(right_des_node)) {
VTR_ASSERT(right_des_chan_type == rr_graph_view.node_type(right_des_node));
des_nodes.push_back(right_des_node);
@ -535,7 +535,7 @@ static void add_rr_graph_block_clock_edges(
/* find the driver clock node through lookup */
RRNodeId src_node =
clk_rr_lookup.find_node(chan_coord.x(), chan_coord.y(), itree, ilvl,
ClockTreePinId(ipin), node_dir);
ClockTreePinId(ipin), node_dir, verbose);
VTR_LOGV(verbose,
"Try to find node '%lu' from clock node lookup (x='%lu' "
"y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n",
@ -548,7 +548,8 @@ static void add_rr_graph_block_clock_edges(
size_t curr_edge_count = edge_count;
for (RRNodeId des_node : find_clock_track2track_node(
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type,
chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) {
chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir,
verbose)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(
@ -593,7 +594,7 @@ static void try_find_and_add_clock_opin2track_node(
const RRGraphView& rr_graph_view, const size_t& layer,
const vtr::Point<int>& grid_coord, const e_side& pin_side,
const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin,
const ClockInternalDriverId& int_driver_id) {
const ClockInternalDriverId& int_driver_id, const bool& verbose) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
for (std::string tap_pin_name :
@ -606,6 +607,8 @@ static void try_find_and_add_clock_opin2track_node(
RRNodeId opin_node = rr_graph_view.node_lookup().find_node(
layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side);
if (rr_graph_view.valid_node(opin_node)) {
VTR_LOGV(verbose, "Connected OPIN '%s' to clock network\n",
tap_pin_name.c_str());
opin_nodes.push_back(opin_node);
}
}
@ -639,7 +642,8 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const size_t& layer, const vtr::Point<int>& sb_coord,
const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin,
const std::vector<ClockInternalDriverId>& int_driver_ids) {
const std::vector<ClockInternalDriverId>& int_driver_ids,
const bool& verbose) {
std::vector<RRNodeId> opin_nodes;
/* Find opins from
* - Grid[x][y+1] on right and bottom sides
@ -663,7 +667,7 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
for (ClockInternalDriverId int_driver_id : int_driver_ids) {
try_find_and_add_clock_opin2track_node(
opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side,
clk_ntwk, clk_pin, int_driver_id);
clk_ntwk, clk_pin, int_driver_id, verbose);
}
}
}
@ -702,9 +706,9 @@ static int add_rr_graph_opin2clk_edges(
vtr::Point<int> des_coord = clk_ntwk.spine_start_point(des_spine);
Direction des_spine_direction = clk_ntwk.spine_direction(des_spine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, ipin, des_spine_direction);
RRNodeId des_node = clk_rr_lookup.find_node(
des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin,
des_spine_direction, verbose);
/* Walk through each qualified OPIN, build edges */
vtr::Point<int> src_coord =
clk_ntwk.spine_switch_point(ispine, switch_point_id);
@ -713,7 +717,7 @@ static int add_rr_graph_opin2clk_edges(
switch_point_id);
for (RRNodeId src_node : find_clock_opin2track_node(
grids, rr_graph_view, layer, src_coord, clk_ntwk, ipin,
int_driver_ids)) {
int_driver_ids, verbose)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(

35
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -97,23 +97,24 @@ static int route_clock_spine_switch_point(
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockSpineId& ispine, const ClockTreePinId& ipin,
const ClockSwitchPointId& switch_point_id, const bool& verbose) {
VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n",
clk_ntwk.spine_name(ispine).c_str());
vtr::Point<int> src_coord =
clk_ntwk.spine_switch_point(ispine, switch_point_id);
ClockSpineId des_spine =
clk_ntwk.spine_switch_point_tap(ispine, switch_point_id);
vtr::Point<int> des_coord = clk_ntwk.spine_start_point(des_spine);
VTR_LOGV(verbose, "Routing switch points from spine '%s' to spine '%s'...\n",
clk_ntwk.spine_name(ispine).c_str(),
clk_ntwk.spine_name(des_spine).c_str());
Direction src_spine_direction = clk_ntwk.spine_direction(ispine);
Direction des_spine_direction = clk_ntwk.spine_direction(des_spine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, ipin, src_spine_direction);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, ipin, des_spine_direction);
RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(),
clk_tree, src_spine_level, ipin,
src_spine_direction, verbose);
RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(),
clk_tree, des_spine_level, ipin,
des_spine_direction, verbose);
VTR_ASSERT(rr_graph.valid_node(src_node));
VTR_ASSERT(rr_graph.valid_node(des_node));
/* Internal drivers may appear at the switch point. Check if there are
@ -200,9 +201,9 @@ static int route_spine_taps(
vtr::Point<int> src_coord = spine_coords[icoord];
Direction src_spine_direction = clk_ntwk.spine_direction(ispine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, ipin, src_spine_direction);
RRNodeId src_node = clk_rr_lookup.find_node(
src_coord.x(), src_coord.y(), clk_tree, src_spine_level, ipin,
src_spine_direction, verbose);
for (RREdgeId edge : rr_graph.edge_range(src_node)) {
RRNodeId des_node = rr_graph.edge_sink_node(edge);
if (rr_graph.node_type(des_node) == IPIN) {
@ -389,12 +390,12 @@ static int rec_expand_and_route_clock_spine(
Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, curr_pin, src_spine_direction);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, curr_pin, des_spine_direction);
RRNodeId src_node = clk_rr_lookup.find_node(
src_coord.x(), src_coord.y(), clk_tree, src_spine_level, curr_pin,
src_spine_direction, verbose);
RRNodeId des_node = clk_rr_lookup.find_node(
des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin,
des_spine_direction, verbose);
VTR_ASSERT(rr_graph.valid_node(src_node));
VTR_ASSERT(rr_graph.valid_node(des_node));
VTR_LOGV(verbose,

18
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -36,7 +36,8 @@ static void update_cluster_pin_with_post_routing_results(
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
const e_side& border_side, const size_t& z, const bool& verbose) {
const e_side& border_side, const size_t& z, const bool& perimeter_cb,
const bool& verbose) {
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
auto physical_tile = device_ctx.grid.get_physical_type(
@ -76,6 +77,13 @@ static void update_cluster_pin_with_post_routing_results(
if (NUM_SIDES == border_side) {
VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0];
} else if (perimeter_cb) {
/* When perimeter connection blcoks are allowed, I/O pins may occur on any
* side but the border side */
VTR_ASSERT(pin_sides.end() ==
std::find(pin_sides.begin(), pin_sides.end(), border_side));
VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0];
} else {
SideManager side_manager(border_side);
VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(),
@ -188,7 +196,8 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose) {
VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& verbose) {
/* Ensure a clean start: remove all the remapping results from VTR's
* post-routing clustering result sync-up */
vpr_clustering_annotation.clear_net_remapping();
@ -219,7 +228,7 @@ void update_pb_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, grid_coord, cluster_blk_id,
NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
verbose);
perimeter_cb, verbose);
}
}
}
@ -250,7 +259,8 @@ void update_pb_pin_with_post_routing_results(
update_cluster_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose);
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, perimeter_cb,
verbose);
}
}
}

3
openfpga/src/base/openfpga_pb_pin_fixup.h
View File

@ -18,7 +18,8 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose);
VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& verbose);
} /* end namespace openfpga */

1
openfpga/src/base/openfpga_pb_pin_fixup_template.h
View File

@ -42,6 +42,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd,
g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(),
openfpga_context.vpr_routing_annotation(),
openfpga_context.mutable_vpr_clustering_annotation(),
g_vpr_ctx.device().arch->perimeter_cb,
cmd_context.option_enable(cmd, opt_verbose));
/* TODO: should identify the error code from internal function execution */

6
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1247,9 +1247,9 @@ static int build_top_module_global_net_from_tile_clock_arch_tree(
Direction entry_dir = clk_ntwk.spine_direction(spine);
t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine);
/* Find the routing resource node of the entry point */
RRNodeId entry_rr_node =
rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree,
clk_ntwk.spine_level(spine), pin, entry_dir);
RRNodeId entry_rr_node = rr_clock_lookup.find_node(
entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine),
pin, entry_dir, false);
/* Get the tile module and instance at the entry point */
const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate(

6
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -1282,9 +1282,9 @@ static int build_top_module_global_net_from_clock_arch_tree(
Direction entry_dir = clk_ntwk.spine_direction(spine);
t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine);
/* Find the routing resource node of the entry point */
RRNodeId entry_rr_node =
rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree,
clk_ntwk.spine_level(spine), pin, entry_dir);
RRNodeId entry_rr_node = rr_clock_lookup.find_node(
entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine),
pin, entry_dir, false);
/* Get the connection block module and instance at the entry point */
vtr::Point<size_t> entry_cb_coord(entry_point.x(), entry_point.y());

2
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -198,6 +198,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@
echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)";
run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@
run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@
run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@
run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@
run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
@ -242,6 +243,7 @@ run-task basic_tests/clock_network/homo_2clock_2layer $@
run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@
run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@
run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@

72
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/clk_arch_1clk_1rst_3layer.xml Normal file
View File

@ -0,0 +1,72 @@
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]">
<spine name="clk_spine_lvl0_botm0" start_x="1" start_y="1" end_x="1" end_y="2">
<switch_point tap="clk_spine_lvl1_right" x="1" y="2"/>
</spine>
<spine name="clk_spine_lvl0_botm1" start_x="2" start_y="1" end_x="2" end_y="2">
<switch_point tap="clk_spine_lvl1_left" x="2" y="2"/>
</spine>
<spine name="clk_spine_lvl1_left" start_x="2" start_y="2" end_x="1" end_y="2">
<switch_point tap="clk_rib_lvl2_x0y2_upper" x="0" y="2"/>
<switch_point tap="clk_rib_lvl2_x0y2_lower" x="0" y="2"/>
<switch_point tap="clk_rib_lvl2_x1y2_upper" x="1" y="2"/>
<switch_point tap="clk_rib_lvl2_x1y2_lower" x="1" y="2"/>
</spine>
<spine name="clk_spine_lvl1_right" start_x="2" start_y="2" end_x="4" end_y="2">
<switch_point tap="clk_rib_lvl2_x2y2_upper" x="2" y="2"/>
<switch_point tap="clk_rib_lvl2_x2y2_lower" x="2" y="2"/>
<switch_point tap="clk_rib_lvl2_x3y2_upper" x="3" y="2"/>
<switch_point tap="clk_rib_lvl2_x3y2_lower" x="3" y="2"/>
<switch_point tap="clk_rib_lvl2_x4y2_upper" x="4" y="2"/>
<switch_point tap="clk_rib_lvl2_x4y2_lower" x="4" y="2"/>
</spine>
<spine name="clk_rib_lvl2_x0y2_upper" start_x="0" start_y="3" end_x="0" end_y="4"/>
<spine name="clk_rib_lvl2_x0y2_lower" start_x="0" start_y="2" end_x="0" end_y="1"/>
<spine name="clk_rib_lvl2_x1y2_upper" start_x="1" start_y="3" end_x="1" end_y="4"/>
<spine name="clk_rib_lvl2_x1y2_lower" start_x="1" start_y="2" end_x="1" end_y="1"/>
<spine name="clk_rib_lvl2_x2y2_upper" start_x="2" start_y="3" end_x="2" end_y="4"/>
<spine name="clk_rib_lvl2_x2y2_lower" start_x="2" start_y="2" end_x="2" end_y="1"/>
<spine name="clk_rib_lvl2_x3y2_upper" start_x="3" start_y="3" end_x="3" end_y="4"/>
<spine name="clk_rib_lvl2_x3y2_lower" start_x="3" start_y="2" end_x="3" end_y="1"/>
<spine name="clk_rib_lvl2_x4y2_upper" start_x="4" start_y="3" end_x="4" end_y="4"/>
<spine name="clk_rib_lvl2_x4y2_lower" start_x="4" start_y="2" end_x="4" end_y="1"/>
<taps>
<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
<spine name="rst_spine_lvl0_botm0" start_x="1" start_y="1" end_x="1" end_y="2">
<switch_point tap="rst_spine_lvl1_right" x="1" y="2"/>
</spine>
<spine name="rst_spine_lvl0_botm1" start_x="2" start_y="1" end_x="2" end_y="2">
<switch_point tap="rst_spine_lvl1_left" x="2" y="2"/>
</spine>
<spine name="rst_spine_lvl1_left" start_x="2" start_y="2" end_x="1" end_y="2">
<switch_point tap="rst_rib_lvl2_x0y2_upper" x="0" y="2"/>
<switch_point tap="rst_rib_lvl2_x0y2_lower" x="0" y="2"/>
<switch_point tap="rst_rib_lvl2_x1y2_upper" x="1" y="2"/>
<switch_point tap="rst_rib_lvl2_x1y2_lower" x="1" y="2"/>
</spine>
<spine name="rst_spine_lvl1_right" start_x="2" start_y="2" end_x="4" end_y="2">
<switch_point tap="rst_rib_lvl2_x2y2_upper" x="2" y="2"/>
<switch_point tap="rst_rib_lvl2_x2y2_lower" x="2" y="2"/>
<switch_point tap="rst_rib_lvl2_x3y2_upper" x="3" y="2"/>
<switch_point tap="rst_rib_lvl2_x3y2_lower" x="3" y="2"/>
<switch_point tap="rst_rib_lvl2_x4y2_upper" x="4" y="2"/>
<switch_point tap="rst_rib_lvl2_x4y2_lower" x="4" y="2"/>
</spine>
<spine name="rst_rib_lvl2_x0y2_upper" start_x="0" start_y="3" end_x="0" end_y="4"/>
<spine name="rst_rib_lvl2_x0y2_lower" start_x="0" start_y="2" end_x="0" end_y="1"/>
<spine name="rst_rib_lvl2_x1y2_upper" start_x="1" start_y="3" end_x="1" end_y="4"/>
<spine name="rst_rib_lvl2_x1y2_lower" start_x="1" start_y="2" end_x="1" end_y="1"/>
<spine name="rst_rib_lvl2_x2y2_upper" start_x="2" start_y="3" end_x="2" end_y="4"/>
<spine name="rst_rib_lvl2_x2y2_lower" start_x="2" start_y="2" end_x="2" end_y="1"/>
<spine name="rst_rib_lvl2_x3y2_upper" start_x="3" start_y="3" end_x="3" end_y="4"/>
<spine name="rst_rib_lvl2_x3y2_lower" start_x="3" start_y="2" end_x="3" end_y="1"/>
<spine name="rst_rib_lvl2_x4y2_upper" start_x="4" start_y="3" end_x="4" end_y="4"/>
<spine name="rst_rib_lvl2_x4y2_lower" start_x="4" start_y="2" end_x="4" end_y="1"/>
<taps>
<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
</taps>
</clock_network>
</clock_networks>

8
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_reset.xml Normal file
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<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="reset"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints>

8
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_resetb.xml Normal file
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<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="resetb" default_value="1"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/repack_pin_constraints.xml Normal file
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<repack_design_constraints>
<!-- Intended to be dummy -->
</repack_design_constraints>

54
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/task.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 3*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=4x4
openfpga_vpr_route_chan_width=32
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_3layer.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_verilog_testbench_port_mapping=
bench1_top = counter
bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
bench1_openfpga_verilog_testbench_port_mapping=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

41
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/task.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command=pb_pin_fixup --verbose
openfpga_vpr_device=2x2
openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_pipelined
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/tile_config.xml Normal file
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<tiles style="top_left"/>