riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1776 from lnis-uofu/xt_doc 

[doc] format to resolve latexpdf build errors; now local build passes
This commit is contained in:
tangxifan 2024-08-03 15:04:09 -07:00 committed by GitHub
parent 328c3873cc c11a2c7381
commit a7920b16a9
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/source/manual/file_formats/tile_config_file.rst
View File

@ -28,6 +28,8 @@ Detailed syntax are presented as follows.
The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
.. _fig_tile_style_top_left:
.. figure:: ./figures/tile_style_top_left.png
@ -37,8 +39,6 @@ Detailed syntax are presented as follows.
An example of top-left style of a tile in FPGA fabric
The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
.. _fig_tile_style_bottom_left:
.. figure:: ./figures/tile_style_bottom_left.png