tangxifan
|
96828e456a
|
[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
|
2021-09-30 22:07:46 -07:00 |
|
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
|
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
|
2021-09-30 21:05:41 -07:00 |
|
tangxifan
|
4526133089
|
[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers
|
2021-09-30 17:01:02 -07:00 |
|
tangxifan
|
43c569b612
|
[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
|
2021-09-30 14:47:21 -07:00 |
|
tangxifan
|
4d8019b7c1
|
[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
|
2021-09-29 22:32:45 -07:00 |
|
tangxifan
|
2d4c200d58
|
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
|
2021-09-29 20:56:02 -07:00 |
|
tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
|
2021-09-29 20:34:25 -07:00 |
|
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
|
2021-09-29 20:21:46 -07:00 |
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tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
|
2021-09-29 16:57:49 -07:00 |
|
tangxifan
|
ac6268d9ae
|
[Engine] Bug fix on compilation errors
|
2021-09-29 16:24:36 -07:00 |
|
tangxifan
|
c5ae93f177
|
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
|
2021-09-29 16:17:40 -07:00 |
|
tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
|
2021-09-28 23:27:47 -07:00 |
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tangxifan
|
7723e00e6c
|
[Engine] Adding the function that builds a shift register module for BL/WLs
|
2021-09-28 22:49:24 -07:00 |
|
tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
|
2021-09-28 17:29:03 -07:00 |
|
tangxifan
|
afd03d7eb7
|
[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
|
2021-09-28 15:56:07 -07:00 |
|
tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
|
tangxifan
|
33e9b27cb8
|
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
|
2021-09-25 20:22:27 -07:00 |
|
tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
|
2021-09-25 18:22:55 -07:00 |
|
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
|
tangxifan
|
386812777c
|
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
|
2021-09-25 12:49:32 -07:00 |
|
tangxifan
|
1a2a2a6e63
|
[FPGA-Bitstream] Relax fabric bitstream address check
|
2021-09-25 12:03:33 -07:00 |
|
tangxifan
|
8b72447dad
|
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
|
2021-09-24 18:07:07 -07:00 |
|
tangxifan
|
a49e3fe57a
|
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
|
2021-09-24 16:30:18 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
8c281a22b0
|
[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
|
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
|
tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
|
2021-09-22 10:20:40 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
2e45a6143b
|
[Engine] Fix a critical bug which causes flatten memory tests failed
|
2021-09-15 15:11:58 -07:00 |
|
tangxifan
|
f2aa31ddb1
|
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
|
2021-09-15 13:45:30 -07:00 |
|
tangxifan
|
061952b7fa
|
[Engine] Bug fix in computing local WLs for GRID/CB/SB
|
2021-09-15 11:51:00 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
|
tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |