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3420 Commits

Author SHA1 Message Date
Lalit Sharma d4c5a5655a Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
Lalit Sharma 6de0954ca5 Uncommenting all benchmarks except 2 that requires multiple clocks 2021-02-19 08:40:26 -08:00
tangxifan 01b9bf2a02 [Doc] Update num_region XML for config protocol 2021-02-18 21:58:30 -07:00
tangxifan e6091fb3ff [Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition 2021-02-18 21:56:30 -07:00
tangxifan bcd8256c59
Merge pull request #243 from lnis-uofu/dev 
Bug fix for truth table creation for wired LUT created by repacking
 2021-02-18 20:44:02 -07:00
tangxifan e08ac1a41e [Test] Deploy synthesizable verilog test to CI 2021-02-18 19:37:45 -07:00
tangxifan e19fc15fec [Test] bug fix in test case 2021-02-18 19:37:45 -07:00
tangxifan affc8cbbc4 [Test] Deploy test to CI 2021-02-18 19:37:45 -07:00
tangxifan 2e88b035ed [Test] Add wire LUT repacker test case 2021-02-18 19:37:44 -07:00
tangxifan 1f097abe99 [Benchmark] Add micro benchmark for FIR filter 2021-02-18 19:37:44 -07:00
tangxifan a5b8b2a64a [Tool] Use dedicated function to identify wire LUT created by repacker 2021-02-18 19:37:44 -07:00
tangxifan aae03482f5 [Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database 2021-02-18 19:37:17 -07:00
ganeshgore 122218dfd3
Merge pull request #244 from lnis-uofu/synth_verilog_test_deployment 
Deploy synthesizable verilog test to CI
 2021-02-18 10:46:19 -07:00
Lalit Sharma 69cdc11ea5 Uncommenting the tests that are running fine 2021-02-18 04:17:12 -08:00
tangxifan a06e7e6c80 Merge branch 'master' into dev 2021-02-17 19:46:09 -07:00
tangxifan 9004e28d47 Merge branch 'master' into synth_verilog_test_deployment 2021-02-17 19:45:35 -07:00
tangxifan 1a23f76bd0
Merge pull request #242 from lnis-uofu/gg_ci_cd_dev 
[Bugfix] Docker regression using master regression scripts
 2021-02-17 19:21:46 -07:00
tangxifan 47cb1cc2d4 [Test] Deploy synthesizable verilog test to CI 2021-02-17 16:13:15 -07:00
tangxifan 61012897cd [Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm 2021-02-17 15:31:20 -07:00
Ganesh Gore 808df8a87e [Bugfix] Docker regression using master regression scripts 2021-02-17 13:23:45 -07:00
tangxifan d85d6e964e
Merge pull request #227 from watcag/master 
Standard-cell flow
 2021-02-17 10:11:34 -07:00
Lalit Sharma 7ee01711c2 Merge remote-tracking branch 'origin/master' into add_quicklogic_tests 2021-02-17 00:06:59 -08:00
ganeshgore 515527f7f1
Merge pull request #238 from lnis-uofu/dev 
Move regression test scripts from workflow to openfpga_flow
 2021-02-17 00:15:03 -07:00
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
tangxifan a819375f69 [Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled 2021-02-16 16:53:13 -07:00
tangxifan 2c2e493739 [Test] Remove quicklogic test from basic tests 2021-02-16 12:29:10 -07:00
tangxifan 9c19e2b365 [Test] Move regression test scripts from workflow to openfpga_flow 2021-02-16 11:55:47 -07:00
ganeshgore 5828e51144
Merge pull request #237 from lnis-uofu/dev 
Move quicklogic regresssion tests to a dedicated CI run
 2021-02-16 11:45:33 -07:00
ganeshgore d4ab913baa
Merge pull request #236 from lnis-uofu/tpagarani_dev 
Tpagarani dev
 2021-02-16 11:04:46 -07:00
tangxifan 62bf0d0c5d [Test] Move quicklogic regresssion tests to a dedicated CI run 2021-02-16 11:00:31 -07:00
Tarachand Pagarani 426b6449d8 change the test to turn off power analysis 2021-02-15 02:45:38 -08:00
Tarachand Pagarani 3a587f663a copy yosys output file in case power analysis setting is off 2021-02-15 02:36:02 -08:00
ganeshgore 45e8baf98f
Merge pull request #235 from lnis-uofu/dev 
Reorganize tutorial documentation
 2021-02-11 16:33:58 -07:00
tangxifan 2eaec13351 [Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section 2021-02-11 14:09:20 -07:00
tangxifan 702bd3bbd5
Merge pull request #231 from lnis-uofu/dev 
Extended LUT Support: Now accept external LUT netlists with embedded custom logic
 2021-02-11 13:57:17 -07:00
tangxifan 184788880c
Merge pull request #224 from lnis-uofu/gg_docs 
[Docs] Added documentation for docker based run and shell shortcuts documentation
 2021-02-11 09:26:29 -07:00
tangxifan c895422014
Merge pull request #234 from lnis-uofu/bump_yosys 
Bumping up latest checkins to yosys sub-module, related to adder_lut4…
 2021-02-11 09:24:49 -07:00
Lalit Sharma c495382416 Bumping up latest checkins to yosys sub-module, related to adder_lut4 inference 2021-02-10 22:22:58 -08:00
tangxifan e683e00032 [HDL] Add disclaimer for the frac_lut4_arith HDL codes 2021-02-10 14:50:11 -07:00
tangxifan 1c4dc9f74b [Doc] Update documentation about the super LUT feature 2021-02-10 11:49:59 -07:00
tangxifan af4cc117fb [Tool] bug fix in spypad lut 2021-02-09 22:53:18 -07:00
tangxifan 9b86f3bb85 Merge branch 'master' into dev 2021-02-09 22:40:45 -07:00
tangxifan b2984b46ee [Tool] Upgrade libopenfpga to support superLUT-related XML syntax 2021-02-09 21:15:57 -07:00
tangxifan be24c904af [Test] Add superLUT test case to CI 2021-02-09 21:15:21 -07:00
tangxifan 22e675148e [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
tangxifan b81b74aa7c [Arch] Patch architecture to support superLUT-related XML syntax 2021-02-09 20:23:32 -07:00
tangxifan 6a0f4f354f [Tool] Support superLUT circuit model in core engine 2021-02-09 20:23:05 -07:00
tangxifan 7dcc14d73f [Arch] Bug fix in the example arch with super LUT 2021-02-09 15:52:22 -07:00
tangxifan 3ae501a5ea [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
tangxifan 1712ee4edb [Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture 2021-02-09 15:41:21 -07:00