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OpenFPGA
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143 Commits

Author SHA1 Message Date
tangxifan 0af6c76239 [engine] code format 2022-10-13 16:27:57 -07:00
tangxifan d1f3338837 [engine] now repacker find only routable pins when given a net to search routing traces 2022-10-13 16:26:45 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan c922259c23 [engine] remove warnings and update vtr 2022-09-19 14:53:30 -07:00
tangxifan 90ddd2ce32 [engine] now get incoming edges for IPINs only from GSB 2022-09-19 14:02:13 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan 0425b00af5 [engine] fixed a bug for frame-based protocols 2022-09-14 16:41:30 -07:00
tangxifan cb89488f76 [engine] now support a custom list for indexing I/O children in each module 2022-09-14 15:54:55 -07:00
tangxifan e5c7a3df9f [engine] syntax 2022-09-07 15:51:54 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan 8d09773e65 [engine] remove unnecessary checks from sb mirror checker 2022-09-07 11:55:08 +08:00
tangxifan e748c7697d [engine] update code comments 2022-09-06 13:51:29 -07:00
tangxifan eab3580f79 [engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity 2022-09-06 13:40:29 -07:00
tangxifan 59440082ed [engine] fixed some syntax errors 2022-09-06 11:55:40 -07:00
tangxifan 2f84ce5955 [engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used 2022-09-06 11:48:21 -07:00
tangxifan 0a6b794ef0 [engine] fixed bugs in subtiles. Revisited the usage of client functions 2022-08-23 12:35:04 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan bf1a81fbb5 [FPGA-bitstream] add timer to computing intensive functions 2022-05-25 14:52:32 +08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan 1c46a92559 [FPGA-Bitstream] Bug fix 2021-10-09 21:59:56 -07:00
tangxifan 7810f376c8 [FPGA-Bitstream] Patch code comments 2021-10-09 21:03:01 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan fdd75c4ec8 [FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks 2021-10-05 17:54:07 -07:00
tangxifan 06b018cfe7 [FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature 2021-10-03 16:05:33 -07:00
tangxifan 3eb601531a [FPGA-Verilog] Many bug fixes 2021-10-02 23:39:53 -07:00
tangxifan f686dd1f60 [FPGA-Bitstream] Do not reverse for now. Previous solution looks correct 2021-10-01 23:12:38 -07:00
tangxifan 198517a898 [FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers 2021-10-01 19:59:50 -07:00
tangxifan 2de6be44d6 [Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled 2021-10-01 18:27:42 -07:00
tangxifan 9e5debabe1 [FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks 2021-10-01 16:23:38 -07:00
tangxifan 4f7ab01bf5 [FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately 2021-10-01 15:47:13 -07:00
tangxifan 96828e456a [FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong 2021-09-30 22:07:46 -07:00
tangxifan 4bdff1554d [Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken 2021-09-30 21:20:56 -07:00
tangxifan 33972fc0ec [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
tangxifan 43c569b612 [FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object 2021-09-30 14:47:21 -07:00
tangxifan 4d8019b7c1 [FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank 2021-09-29 22:32:45 -07:00
tangxifan 834bdd2b07 [Engine] Updating fabric generator to support BL/WL shift registers. Still WIP 2021-09-28 17:29:03 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 33e9b27cb8 [Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs 2021-09-25 20:22:27 -07:00
tangxifan 3cf31f1565 [Engine] Fixed bugs 2021-09-25 18:22:55 -07:00
tangxifan 386812777c [FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs 2021-09-25 12:49:32 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan 2de4a460a8 [Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator 2021-09-24 15:15:32 -07:00
tangxifan 8c281a22b0 [Engine] Add check codes to validate circuit models for BL/WL protocols 2021-09-23 14:39:16 -07:00
tangxifan 962acda810 [Engine] Bug fix in fabric key generation when computing configurable children 2021-09-22 11:09:46 -07:00
tangxifan ad432e4d95 [Engine] Bug fix in finding the start index of BL/WL for each column/row; 2021-09-22 10:20:40 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00