AurelienUoU
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9f16bb5998
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Synthax correction 2 -> new line
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2019-07-08 10:36:58 -06:00 |
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AurelienUoU
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c1ae3059c4
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Correct synthax error
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2019-07-08 10:32:39 -06:00 |
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AurelienUoU
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b2717abc3e
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Replace obsolete example folder and start tutorial
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2019-07-08 10:30:26 -06:00 |
Baudouin Chauviere
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df0a3d23a3
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Correction top module
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2019-07-08 10:23:14 -06:00 |
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Baudouin Chauviere
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ae05c553d5
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Top module done
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2019-07-08 09:48:33 -06:00 |
tangxifan
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fb064daded
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Merge branch 'tileable_routing' into dev
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2019-07-05 21:15:59 -06:00 |
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tangxifan
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76fefdb876
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bug fixing in Fc_in and be serious in the performance of rr_graph
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2019-07-05 16:23:15 -06:00 |
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tangxifan
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c62762ce59
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bug fixing in assign ipins to tracks using Fc_in
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2019-07-05 13:42:22 -06:00 |
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AurelienUoU
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df53f6da2c
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Updates FPGA-Verilog command lines
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2019-07-05 13:41:34 -06:00 |
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tangxifan
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64d8e9663a
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minor fix to satisfy Fc_in and Fc_out
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2019-07-05 13:13:35 -06:00 |
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AurelienUoU
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b4a78abc04
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Update doc
Merge remote-tracking branch 'origin/heterogeneous' into dev
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2019-07-05 12:25:37 -06:00 |
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AurelienUoU
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9e99048815
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Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
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2019-07-05 11:56:02 -06:00 |
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AurelienUoU
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27dbc527a0
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Update Readme
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2019-07-05 11:06:55 -06:00 |
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AurelienUoU
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f56adc6815
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Update documentation
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2019-07-05 10:20:16 -06:00 |
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tangxifan
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3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
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c8ceb8f7d5
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update fpga_flow.pl
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2019-07-04 12:23:11 -06:00 |
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tangxifan
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5a50fa84d1
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keep updating fpga_flow.pl to use system call
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2019-07-03 22:57:43 -06:00 |
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tangxifan
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d64aeef5c4
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add profiling to routing compact process
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2019-07-03 16:57:34 -06:00 |
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tangxifan
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1a1da30ae9
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fixed a critical bug in using tileable route chan W
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2019-07-03 16:46:43 -06:00 |
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tangxifan
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6b894640c7
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bug fixing in fpga_flow.pl
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2019-07-03 14:59:05 -06:00 |
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tangxifan
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b79d276ea9
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add profiling to fpga_x2p_setup
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2019-07-03 14:44:54 -06:00 |
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tangxifan
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d5137eb424
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-03 14:31:18 -06:00 |
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tangxifan
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5195faab8b
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:30:39 -06:00 |
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tangxifan
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4f3cb0bdf3
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added tileable routing chanW adaption to fixed W router
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2019-07-03 14:29:50 -06:00 |
Ganesh Gore
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443a73954f
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Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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tangxifan
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c9743e84da
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-03 14:12:47 -06:00 |
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tangxifan
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45b00e0881
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:11:45 -06:00 |
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tangxifan
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a539c6a2a7
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bug fixing in fpga_flow.pl
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2019-07-03 14:11:14 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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AurelienUoU
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e13c703709
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Upload recent commit
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-03 13:09:34 -06:00 |
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AurelienUoU
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43e9d8afd1
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Add compact routing hierarchy option in fpga_flow
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2019-07-03 13:08:49 -06:00 |
|
Ganesh Gore
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3c36a51011
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Added 'rewrite_path_in_file' back to repository
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2019-07-03 12:49:25 -06:00 |
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Ganesh Gore
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53486b8a89
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Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
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2019-07-03 12:30:56 -06:00 |
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tangxifan
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570f9495e6
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Merge branch 'tileable_routing' into dev
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2019-07-03 12:13:48 -06:00 |
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tangxifan
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0c3e8bb70a
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add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
|
AurelienUoU
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e0793c891a
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Update demo
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2019-07-03 12:04:55 -06:00 |
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tangxifan
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ea7e119313
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Merge branch 'tileable_routing' into dev
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2019-07-03 10:37:27 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
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2019-07-03 10:33:02 -06:00 |
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tangxifan
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547c479d84
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Merge branch 'tileable_routing' into dev
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2019-07-02 16:26:51 -06:00 |
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tangxifan
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4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
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2019-07-02 15:34:59 -06:00 |
|
Baudouin Chauviere
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b08513d902
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Big chunk added on the routing part of the explicit mapping
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2019-07-02 14:12:42 -06:00 |
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tangxifan
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3e2a4917f5
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Merge branch 'tileable_routing' into dev
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2019-07-02 10:37:25 -06:00 |
|
AurelienUoU
|
60f7ab0465
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Start heterogeneous dev
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2019-07-02 10:16:10 -06:00 |
|
Baudouin Chauviere
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8f5ad2eb67
|
Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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tangxifan
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95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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e2b7636229
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Merge pull request #6 from LNIS-Projects/multimode_clb
Multimode clb
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2019-07-02 09:48:24 -06:00 |
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tangxifan
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44301bfd77
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updated SPICE generator to avoid issues on clb2clb_direct
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2019-07-02 09:01:52 -06:00 |
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tangxifan
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5b25bbb120
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bug fixed for direct connection in CBs and direct connection in top netlist
|
2019-07-01 17:25:00 -06:00 |
|
Baudouin Chauviere
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f189ef1d8f
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Done with the submodules
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2019-07-01 14:24:09 -06:00 |
|
Baudouin Chauviere
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370ce23646
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Mux explicit verilog done
|
2019-07-01 13:58:24 -06:00 |