d842026672
Disabling verilog testbench generation for quicklogic tests
2021-02-21 21:58:23 -08:00
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
d4c5a5655a
Removing blif file as well as and2 testcase
2021-02-19 08:55:17 -08:00
6de0954ca5
Uncommenting all benchmarks except 2 that requires multiple clocks
2021-02-19 08:40:26 -08:00
69cdc11ea5
Uncommenting the tests that are running fine
2021-02-18 04:17:12 -08:00
7ee01711c2
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
2021-02-17 00:06:59 -08:00
515527f7f1
Merge pull request #238 from lnis-uofu/dev
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Move regression test scripts from workflow to openfpga_flow
2021-02-17 00:15:03 -07:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
a819375f69
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
2021-02-16 16:53:13 -07:00
2c2e493739
[Test] Remove quicklogic test from basic tests
2021-02-16 12:29:10 -07:00
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00
5828e51144
Merge pull request #237 from lnis-uofu/dev
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Move quicklogic regresssion tests to a dedicated CI run
2021-02-16 11:45:33 -07:00
d4ab913baa
Merge pull request #236 from lnis-uofu/tpagarani_dev
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Tpagarani dev
2021-02-16 11:04:46 -07:00
62bf0d0c5d
[Test] Move quicklogic regresssion tests to a dedicated CI run
2021-02-16 11:00:31 -07:00
426b6449d8
change the test to turn off power analysis
2021-02-15 02:45:38 -08:00
3a587f663a
copy yosys output file in case power analysis setting is off
2021-02-15 02:36:02 -08:00
45e8baf98f
Merge pull request #235 from lnis-uofu/dev
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Reorganize tutorial documentation
2021-02-11 16:33:58 -07:00
2eaec13351
[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
2021-02-11 14:09:20 -07:00
702bd3bbd5
Merge pull request #231 from lnis-uofu/dev
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Extended LUT Support: Now accept external LUT netlists with embedded custom logic
2021-02-11 13:57:17 -07:00
184788880c
Merge pull request #224 from lnis-uofu/gg_docs
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[Docs] Added documentation for docker based run and shell shortcuts documentation
2021-02-11 09:26:29 -07:00
c895422014
Merge pull request #234 from lnis-uofu/bump_yosys
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Bumping up latest checkins to yosys sub-module, related to adder_lut4…
2021-02-11 09:24:49 -07:00
c495382416
Bumping up latest checkins to yosys sub-module, related to adder_lut4 inference
2021-02-10 22:22:58 -08:00
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
af4cc117fb
[Tool] bug fix in spypad lut
2021-02-09 22:53:18 -07:00
9b86f3bb85
Merge branch 'master' into dev
2021-02-09 22:40:45 -07:00
b2984b46ee
[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
2021-02-09 21:15:57 -07:00
be24c904af
[Test] Add superLUT test case to CI
2021-02-09 21:15:21 -07:00
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00
b81b74aa7c
[Arch] Patch architecture to support superLUT-related XML syntax
2021-02-09 20:23:32 -07:00
6a0f4f354f
[Tool] Support superLUT circuit model in core engine
2021-02-09 20:23:05 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
3ae501a5ea
[Test] Update test case to use dedicated eblif file
2021-02-09 15:51:57 -07:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
c2b68606c9
[Bugfix] Added shell globstar
2021-02-08 14:07:01 -07:00
1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev
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[Flow] Support multi-user environment for running task
2021-02-08 12:43:57 -07:00
6761df6d9d
[Bugfix] Reverted setting OPENFPGA_PATH
2021-02-08 12:36:50 -07:00
7b8fd55916
[Bugfix] Task name in regression flow
2021-02-08 12:06:36 -07:00
12e4fa07a2
[bugfix] OPENFPGA_PATH location
2021-02-08 11:57:15 -07:00
9c5e1b1478
[CI] Updated test
2021-02-08 11:11:00 -07:00
18070954d8
[CI] Moved test to basic test
2021-02-08 10:20:57 -07:00
80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup
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[Flow] ACE is optional during flow script, only runs when power estimation is on
2021-02-08 10:08:47 -07:00
c35cf72489
[Docs] Added OpenFPGA shortcut commands docs
2021-02-07 23:53:05 -07:00
cbd2064f59
[Docs] Updated docker based run documentation
2021-02-07 23:33:25 -07:00
080d21c9f1
[Flow] Updated shortcuts shell script
2021-02-07 22:35:13 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
9020577e80
Support SVG in Sphinx Latex building ( #220 )
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* [Doc] Try use image converter instead of svg2pdf which requires more dependencies
* [Doc] Add img converter to conf.py
* [Doc] Bug fix in importing imgconverter package
* [Doc] Try to fix the bug when importing python packages
* [Doc] bug fix
* [Doc] Try to use imgconverter rather than cairo
* [Doc] Add svg to latex config in sphinx configuration file
* [Doc] Try cairo svg converter
* [Doc] Correct bugs in compiling latexpdf
* [Doc] Use latest image in building readthedocs
* [Doc] Now use readthedocs docker image in building online documentation
* [Doc] Correct typo in readthedocs setting
* [Doc] Try to use inkscape converter as imgconverter converted SVG to black images
* [Doc] Try RSVG
2021-02-07 18:53:16 -07:00
Lalit Sharma
ganeshgore
tangxifan
Tarachand Pagarani