812af4f722
[arch] add arch that supports negative edge triggered flip-flop
2022-05-09 16:32:01 +08:00
c8ff3fc8dc
[test] add regression test to validate compilation of openfpga cell library files
2022-05-09 16:00:51 +08:00
d4992fd9ad
[HDL] Add a multi-mode ff which can support posedge and negedge
2022-05-09 15:52:17 +08:00
fdaf97e60d
[Test] Update test case by using GPIO with config_done signals
2022-02-24 09:49:34 -08:00
fcaff28e24
[HDL] Add a new IO cell with config_done support
2022-02-24 09:46:55 -08:00
b27a04eb24
[Test] Now test case has a config done CCFF
2022-02-23 22:07:11 -08:00
ff264c00a2
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-31 11:51:34 -07:00
0a449cc24c
[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
2021-10-30 11:45:01 -07:00
0b06820177
[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
2021-10-01 17:06:35 -07:00
2ce2fb269a
[HDL] Added a different FF model which is designed to drive WLW only
2021-09-28 12:35:13 -07:00
6469ee3048
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
2021-09-28 12:21:54 -07:00
d36d1ebee2
[HDL] Temporarily disable WLR func in primitive HDL modeling
2021-09-20 17:07:51 -07:00
5c1c428ea5
[HDL] Updated cell library with the SRAM cell with Read Enable signal
2021-09-20 11:13:36 -07:00
477e535344
[HDL] Added a multi-mode FF design with configurable asynchronous reset
2021-07-02 11:13:03 -06:00
75a12e55de
[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
2021-06-29 11:40:22 -06:00
63309ba72b
[HDL] Patch dpram cell
2021-04-27 23:42:31 -06:00
e67095edd2
[HDL] Add 16k-bit dual port ram verilog
2021-04-27 19:55:16 -06:00
8b8096f3a8
[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
2021-04-24 14:57:09 -06:00
c44688739d
[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks
2021-04-23 22:12:26 -06:00
adfea88be2
[HDL] Rename multi-mode DFF module
2021-04-21 20:06:03 -06:00
62497549b6
[HDL] Add multi-mode DFF module
2021-04-21 20:04:40 -06:00
108c84a022
[HDL] Add HDL for 8-bit single-mode multiplier
2021-03-23 15:36:09 -06:00
f9dc7c1b54
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
2021-03-17 15:15:22 -06:00
bb2a02c9ad
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[ https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v ]
2021-03-11 15:23:14 -07:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
95fe4d7dae
adding dff synth
2021-02-09 10:34:54 -05:00
d7967da328
bugfix in alt
2021-02-08 23:04:00 -05:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
cf154d8bb9
no need for dff*, but need tap_buf4
2021-02-08 22:29:55 -05:00
e14c0bf0c4
no need for dff*, but need tap_buf4
2021-02-08 22:28:42 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
709ee1b842
[HDL] Update dff netlist for SCFF used in configuration chain
2021-01-04 17:17:35 -07:00
722a9bcf63
[HDL] Add scan-chain DFF cell with configuration enable signal
2021-01-04 14:31:26 -07:00
ff53d2c375
[HDL] Add new Scan-chain DFF cell
2020-11-30 17:54:10 -07:00
ad703ad85b
[HDL] Add new gpio cell with protection circuitry
2020-11-30 17:52:39 -07:00
5eb04e6fff
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
2020-11-22 20:53:32 -07:00
1a79a55646
[HDL] Add DFF cell with reset but only 1 output
2020-11-06 11:19:19 -07:00
7d46b35296
[HDL] Add single-output DFF HDL
2020-11-06 10:18:37 -07:00
c074e88dcd
[HDL] Add embedded I/O HDL for Caravel SoC interface
2020-11-04 17:09:59 -07:00
c036c87d6d
[HDL] Bug fix in the GP output pad
2020-11-02 18:37:53 -07:00
7e9e0ec9d4
[HDL] Bug fix in I/O HDL code
2020-11-02 15:15:45 -07:00
tangxifan
Nachiket Kapre
AurelienAlacchi