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OpenFPGA
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781 Commits

Author SHA1 Message Date
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 094b3e9b90 [Script] Use parameters in template yosys script supporting BRAMs 2021-03-16 19:51:48 -06:00
tangxifan cea43c2c45 [HDL] Add SPRAM module to generic yosys tech lib for openfpga usage 2021-03-16 18:04:31 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan 84778bd38d [Script] Add new yosys script to support architectures with BRAMs 2021-03-16 16:52:18 -06:00
tangxifan 090f483a11 [Script] Now task-run script support the use of env variables openfpga_path in yosys scripts 2021-03-16 16:45:57 -06:00
tangxifan 76837e02e6 [Script] Rename yosys script supporting bram and restructure techlib files 2021-03-16 16:16:53 -06:00
Tarachand Pagarani db8ea86b2f update tests to use no_ff_map and remove tests that need async set/reset for now 2021-03-10 10:04:45 -08:00
Tarachand Pagarani 608bd1f658 comment out desings that utilize local async reset/preset 2021-03-09 19:24:01 -08:00
Tarachand Pagarani 7f4c20ff33 comment out desings that utilize local async reset/preset 2021-03-09 10:37:06 -08:00
Tarachand Pagarani c4b83aeaa9 bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type 2021-03-09 00:46:40 -08:00
tangxifan 906d2fa72d
Merge branch 'master' into shift_reg 2021-03-08 09:24:29 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
Lalit Sharma 2b2acae757 Adding command to generate verilog file out of yosys run 2021-03-05 04:07:02 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
Lalit Sharma 0038496d9c Replacing -openfpga with -family qlf_k4n8 2021-02-28 21:08:47 -08:00
tangxifan b4b6ada06f [Script] Correct bugs in example scripts using default_net_type 2021-02-28 16:31:44 -07:00
tangxifan 86930d63d3 [Test] Deploy new test to CI 2021-02-28 16:18:46 -07:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 8cc2c7d924 [Script] Bug fix for default net type example script 2021-02-28 12:35:44 -07:00
tangxifan 6d419fed41 [Test] Deploy verilog default net wire type test case to CI 2021-02-28 12:33:48 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan 0723b79bce [Script] Add example script for verilog default net type 2021-02-28 12:29:56 -07:00
tangxifan 27200e3daa [Test] Update regression test cases for fpga verilog 2021-02-28 12:24:36 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan ae05871b1f [Script] Remove default net type from an example script; Limit it to some test cases 2021-02-28 12:19:14 -07:00
tangxifan d7eb159726 [Script] Add default net type option to example openfpga shell scripts 2021-02-28 12:08:30 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 744d87cb4e [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues 2021-02-26 09:34:52 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan 4c2a88e27f [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed 2021-02-24 11:51:10 -07:00
tangxifan 0ce9b66c75 [Arch] Add a dummy adder lut circuit model to support HDL simulation 2021-02-24 10:09:44 -07:00
tangxifan 86a602d381 [Test] Deploy new test to CI 2021-02-23 19:55:07 -07:00
tangxifan a62786986b [Test] Turn off verification in adder lut test temporarily 2021-02-23 19:03:25 -07:00
tangxifan ad25944e59 [Arch] Patched superLUT architecture example when trying adder8 synthesis script 2021-02-23 19:00:27 -07:00
tangxifan 53df7f69e7 [Test] Bug fix in the test case using lut adder 2021-02-23 16:59:46 -07:00
tangxifan db71cc8a16 [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
tangxifan 19f6b221b1 [Test] Rework comments on runtime 2021-02-22 15:25:57 -07:00
tangxifan 4803b0ce42 [Test] Add test case for sdc controller 2021-02-22 15:02:14 -07:00
tangxifan c7a9a4e896 [Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs 2021-02-22 15:01:50 -07:00
tangxifan ca135f3325 [Arch] Add flagship architecture with 8-clock 2021-02-22 15:01:18 -07:00