tangxifan
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4f96680e1f
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[core] adapt to side var changes
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2024-10-07 14:20:48 -07:00 |
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tangxifan
|
772da3006b
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[core] code format
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2024-05-18 22:19:17 -07:00 |
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tangxifan
|
304f34525e
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[core] syntax
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2024-05-18 22:17:52 -07:00 |
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tangxifan
|
717906ea17
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[core] code format
|
2023-08-25 15:13:39 -07:00 |
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tangxifan
|
89b392a51f
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[core] adapt changes in is_sb_exist()
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2023-08-25 15:13:00 -07:00 |
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tangxifan
|
94d80a9b7c
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[core] code format
|
2023-08-08 16:28:56 -07:00 |
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tangxifan
|
867da98d3f
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[core] update to use latest api from vpr upstream
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2023-08-08 16:28:19 -07:00 |
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tangxifan
|
d3895c3dc0
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[core] code format
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2023-08-03 17:34:25 -07:00 |
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tangxifan
|
f4cbc95053
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[core] syntax
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2023-08-03 17:33:57 -07:00 |
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tangxifan
|
de6956530f
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[core] disable pnr sdc for tile-based fabric
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2023-07-25 15:38:41 -07:00 |
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tangxifan
|
a4f26798b0
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[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc
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2023-06-19 11:59:48 -07:00 |
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tangxifan
|
327f7f4dab
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[core] now adapt to latest API of DeviceGrid
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2023-06-07 18:54:48 -07:00 |
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tangxifan
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e2debd2dde
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[engine] add missing header files after coding formatter sorts the include files
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2022-10-06 18:08:57 -07:00 |
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tangxifan
|
6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
|
d1edc51165
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[engine] clean up header files that include rr_graph_obj
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2022-08-23 18:38:21 -07:00 |
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tangxifan
|
0a6b794ef0
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[engine] fixed bugs in subtiles. Revisited the usage of client functions
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2022-08-23 12:35:04 -07:00 |
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tangxifan
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e0ae851e28
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[engine] correcting compilation errors due to vpr upgrade
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2022-08-17 16:25:12 -07:00 |
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tangxifan
|
0c329866da
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[engine] Use RRGraphView in openfpga source codes
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2022-08-16 16:48:32 -07:00 |
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tangxifan
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33064ca4cf
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[FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands
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2022-01-25 15:51:28 -08:00 |
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tangxifan
|
7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
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tangxifan
|
ce3c80f499
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Merge branch 'master' into dev
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2021-06-23 09:15:03 -06:00 |
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tangxifan
|
1fd399736d
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[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
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2021-05-27 10:26:20 -06:00 |
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tangxifan
|
902c4cf9e9
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Merge branch 'master' into dev
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2021-03-18 15:14:14 -06:00 |
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tangxifan
|
c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
|
07257d0ff0
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[Tool] Patch wrong paths in FPGA-SDC
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2021-03-13 10:58:03 -07:00 |
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tangxifan
|
6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
|
2021-02-09 20:23:05 -07:00 |
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tangxifan
|
87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
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tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
81e56d45d6
|
[Tool] Update FPGA-SDC to use the new data structure for global ports
|
2020-11-10 21:17:17 -07:00 |
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tangxifan
|
c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
|
4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
|
2020-11-03 13:21:50 -07:00 |
|
tangxifan
|
e4d974c5c8
|
[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
|
721bcce373
|
[Tool] Change analysis SDC file name to track netlist name
|
2020-10-10 17:43:35 -06:00 |
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tangxifan
|
1b55dfb441
|
hotfix on treating the dangling ports in pb_graph for analysis SDC generator
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2020-07-09 23:28:42 -06:00 |
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tangxifan
|
0a3c746fb1
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now split CB module bus ports into lower/upper parts
|
2020-07-01 14:37:13 -06:00 |
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tangxifan
|
05187f8aa4
|
use typedef to short the module pin information
|
2020-06-30 18:07:22 -06:00 |
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tangxifan
|
2e7684b746
|
adapt bus ports in connection block module builder
|
2020-06-30 17:50:53 -06:00 |
|
tangxifan
|
2ef083c49d
|
adapt SB module builder to use bus ports
|
2020-06-30 16:02:40 -06:00 |
|
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
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tangxifan
|
8915d10d27
|
add verbose output option to configure port disable timing writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
6177921d4c
|
bug fixed in configure port disable timing. Now we disable the right ports of LUTs
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
067d09f954
|
bug fix for configure port disable_timing writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
13f591cacf
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add new command to disable timing for configure ports of programmable modules
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
ae9f1fbd90
|
critical bug fixed in the disable MUX output
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
99751b84f5
|
bug fix in configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
02e86c565a
|
bug fix in configuration chain SDC writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
4c0953415b
|
add configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
dad99d13a2
|
bug fixed in SDC timing writer for primitive pb_type
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
b8a79c563d
|
bug fix in the SDC port generation
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
84d24ad075
|
bug fix in pnr sdc grid writer for module paths in hierarchical view
|
2020-06-11 19:31:05 -06:00 |