tangxifan
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9b86f3bb85
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Merge branch 'master' into dev
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2021-02-09 22:40:45 -07:00 |
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tangxifan
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22e675148e
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[HDL] Add HDL codes for a super LUT with embedded carry logic
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2021-02-09 21:13:22 -07:00 |
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tangxifan
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b81b74aa7c
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[Arch] Patch architecture to support superLUT-related XML syntax
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2021-02-09 20:23:32 -07:00 |
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tangxifan
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7dcc14d73f
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[Arch] Bug fix in the example arch with super LUT
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2021-02-09 15:52:22 -07:00 |
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tangxifan
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3ae501a5ea
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[Test] Update test case to use dedicated eblif file
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2021-02-09 15:51:57 -07:00 |
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tangxifan
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1712ee4edb
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[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
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2021-02-09 15:41:21 -07:00 |
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tangxifan
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2b51b36dd6
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[Test] Now use the super LUT arch in the test case
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2021-02-09 15:27:44 -07:00 |
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tangxifan
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56284059de
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[Test] Add a test case for a super LUT
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2021-02-09 15:25:32 -07:00 |
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tangxifan
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304b26c97f
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[Arch] Add example architectures for superLUT circuit model
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2021-02-09 15:11:12 -07:00 |
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tangxifan
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1ce94040da
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Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
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2021-02-08 12:43:57 -07:00 |
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tangxifan
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80a4872ba0
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Merge pull request #222 from lnis-uofu/gg_cleanup
[Flow] ACE is optional during flow script, only runs when power estimation is on
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2021-02-08 10:08:47 -07:00 |
Ganesh Gore
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ede5f8ed58
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[Flow] Support multi-user enviroment for running task
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2021-02-07 22:11:04 -07:00 |
AurelienAlacchi
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00fc3d7622
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Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
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2021-02-05 09:53:28 -07:00 |
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ganeshgore
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ee14c15e58
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Merge pull request #212 from lnis-uofu/soft_adder_lut_support
Support overloading LUT bitstream from attributes in .eblif file format
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2021-02-04 21:55:02 -07:00 |
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tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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dc09c47411
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[Arch] Remove packable from architecture files and replace with disable_packing
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2021-02-04 18:03:56 -07:00 |
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tangxifan
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224bf6c686
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Merge branch 'master' into dev
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2021-02-04 17:21:15 -07:00 |
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tangxifan
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66bc370c4d
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[Arch] Use disable_packing in architecture library
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2021-02-04 16:29:03 -07:00 |
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tangxifan
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a4c266d59a
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[Arch] Add pack patterns for soft adders; Still fail in packing
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2021-02-03 19:11:15 -07:00 |
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Ganesh Gore
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6cdc31f073
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[Flow] ACE is optional duign flow script
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2021-02-03 19:07:48 -07:00 |
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tangxifan
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cac1160bf7
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[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
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2021-02-03 11:20:56 -07:00 |
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Ganesh Gore
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df4a397470
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[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
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tangxifan
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4c825b27b3
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[Benchmark] Change to use adder lut4 to be consistent with architecture
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2021-02-03 09:37:48 -07:00 |
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tangxifan
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31441c0b64
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[Test] Deploy adder_8 to soft adder test
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2021-02-03 09:26:38 -07:00 |
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tangxifan
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05d63567d0
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[Benchmark] Use latest adder eblif file
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2021-02-03 09:21:38 -07:00 |
Lalit Sharma
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ebe66dea35
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Bumping up latest yosys changes related to adder tech mapping
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2021-02-03 14:30:06 +05:30 |
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tangxifan
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2c06960e4f
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[Benchmark] Add subckt definition to micro benchmark and2.eblif
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2021-02-02 15:51:16 -07:00 |
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tangxifan
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021520783b
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[Arch] Add dummy timing info to adder_lut4 and carry_follower model
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2021-02-02 15:49:43 -07:00 |
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tangxifan
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dc320182b0
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[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
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2021-02-02 15:04:43 -07:00 |
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tangxifan
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8e36ed1ab6
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[Test] Update task configuration to use and2 eblif
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2021-02-02 15:01:15 -07:00 |
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tangxifan
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62803dc044
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[Benchmark] Add eblif example for and2 benchmark
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2021-02-02 14:59:31 -07:00 |
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tangxifan
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5e2847bc41
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[Test] Update test case to use eblif file
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2021-02-02 09:33:41 -07:00 |
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tangxifan
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39e6f62d91
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[Benchmark] Use eblif in naming the adder_8 micro benchmark
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2021-02-02 09:32:42 -07:00 |
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tangxifan
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d3397f6936
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[Script] Remove activity from bitstream setting example script
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2021-02-02 09:25:36 -07:00 |
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tangxifan
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9ff5e7926b
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[Test] Update test case to use the adder benchmark
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2021-02-02 09:24:39 -07:00 |
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tangxifan
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7f14dfbe87
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[Script] Add example script to use bitstream setting
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2021-02-02 09:18:08 -07:00 |
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tangxifan
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04594cb7ab
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[Test] Adapt bitstream annotatin file to parser's requirement
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2021-02-01 17:38:36 -07:00 |
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tangxifan
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280c9620aa
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[Test] Add an example bitstream annotation file
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2021-02-01 16:01:21 -07:00 |
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tangxifan
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a6354fab7c
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[Arch] Decide to move external bitstream definition to a separated XML file
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2021-02-01 15:57:44 -07:00 |
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tangxifan
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df88e2adc0
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[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
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2021-02-01 14:26:11 -07:00 |
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tangxifan
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10302752a7
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[Arch] Bug fix in architecture. Now soft adder modes are accepted
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2021-02-01 13:43:39 -07:00 |
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tangxifan
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d8927e12e8
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[Arch] Add soft adder operating mode to test architecture
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2021-02-01 12:25:37 -07:00 |
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tangxifan
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7f0f7a1c70
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[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
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2021-02-01 12:05:04 -07:00 |
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tangxifan
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b215b868c1
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[HDL] Bug fix in HDL netlist due to port name mismatching
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2021-02-01 11:35:25 -07:00 |
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tangxifan
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e4abe263c3
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[Arch] Bug fix
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2021-02-01 11:29:27 -07:00 |
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tangxifan
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fb05e1a938
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[Arch] bug fix due to using openfpga cell library
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2021-02-01 11:27:21 -07:00 |
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tangxifan
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940dce469a
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[Test] Bug fix for test case configuration
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2021-02-01 11:19:47 -07:00 |
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tangxifan
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a80acfb547
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[Test] Add new test case to CI script
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2021-02-01 11:16:12 -07:00 |
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tangxifan
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af630dab1e
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[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
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2021-02-01 10:53:38 -07:00 |
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tangxifan
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9cce411eda
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[Test] Add adder test cases
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2021-02-01 10:42:24 -07:00 |