tangxifan
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f9f7d42d93
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[core] add port side attribute and set them when buidling grid/cb/sb modules
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2024-04-10 17:10:06 -07:00 |
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tangxifan
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37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
|
bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |
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tangxifan
|
d3895c3dc0
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[core] code format
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2023-08-03 17:34:25 -07:00 |
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tangxifan
|
87f2822ef8
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[core] working on logical and physical children
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2023-08-02 19:46:27 -07:00 |
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tangxifan
|
470ab84489
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[core] developing group config block support for routing module
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2023-08-01 22:57:22 -07:00 |
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tangxifan
|
53050b94ab
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[core] developing memory group modules in grid modules
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2023-08-01 17:50:03 -07:00 |
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tangxifan
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23643f3fb1
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[core] developing the physical memory block builder
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2023-07-31 22:57:26 -07:00 |
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tangxifan
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3745897ff6
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[core] fixed a few bugs
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2023-07-24 16:10:29 -07:00 |
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tangxifan
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da36b735c6
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[core] syntax
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2023-07-24 12:13:45 -07:00 |
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tangxifan
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93c5a68592
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[core] developing top-level nets for tiles
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2023-07-21 23:21:53 -07:00 |
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tangxifan
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6607bb7e48
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[core] now fpga verilog supports tile modules
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2023-07-18 22:35:22 -07:00 |
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tangxifan
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ba4b7e3522
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[core] developing tile module builder
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2023-07-16 15:18:09 -07:00 |
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tangxifan
|
cef573529d
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[core] now fpga verilog can output fpga core netlist
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2023-06-18 21:17:50 -07:00 |
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tangxifan
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c7ade72200
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[core] code complete for the core wrapper creator. Start debugging
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2023-06-18 19:17:42 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
|
7723e00e6c
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[Engine] Adding the function that builds a shift register module for BL/WLs
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2021-09-28 22:49:24 -07:00 |
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tangxifan
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18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
|
36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
|
b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
|
c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
|
956b9aca01
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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tangxifan
|
2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
|
cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
|
6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
|
6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
|
5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
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tangxifan
|
721bcce373
|
[Tool] Change analysis SDC file name to track netlist name
|
2020-10-10 17:43:35 -06:00 |
|
tangxifan
|
2603836111
|
split logical tile netlists to keep good Verilog hierarchy
|
2020-07-24 12:53:21 -06:00 |
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tangxifan
|
be5966475e
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formulate file name, module name and instance name to be consistent
|
2020-07-24 12:23:27 -06:00 |
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tangxifan
|
1f38e17111
|
bug fix for naming conflicts in mux local encoder and architecture decoders
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2020-07-03 14:12:13 -06:00 |
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tangxifan
|
0a3c746fb1
|
now split CB module bus ports into lower/upper parts
|
2020-07-01 14:37:13 -06:00 |
|
tangxifan
|
2e7684b746
|
adapt bus ports in connection block module builder
|
2020-06-30 17:50:53 -06:00 |
|
tangxifan
|
2ef083c49d
|
adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
|
tangxifan
|
675a59ecb8
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Move fpga_bitstream to the libopenfpga library and add XML reader
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2020-06-20 18:25:17 -06:00 |
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tangxifan
|
0bee70bee6
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finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0e16ee1030
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add configuration bus nets for memory bank decoders at top module
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fbe05963e0
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
68b7991a46
|
bug fixed for sdc on memory blocks
|
2020-04-21 13:37:56 -06:00 |
|
tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
|
2020-04-05 17:26:44 -06:00 |
|
tangxifan
|
37423729ec
|
bug fixing for naming the duplicated pins
|
2020-03-07 15:44:57 -07:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
e37ac8a098
|
add grid module Verilog writer
|
2020-02-16 16:04:41 -07:00 |
|
tangxifan
|
072965cd64
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
|
tangxifan
|
f11832b8cf
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |