tangxifan
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8d57808d07
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add missing files for micro benchmarks
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2020-03-20 11:08:55 -06:00 |
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tangxifan
|
808853db0b
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critical bug fixed for find proper pb_route traceback
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2020-03-13 12:26:37 -06:00 |
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tangxifan
|
81e5af464e
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improve lb_route to avoid routing combinational loops
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2020-03-12 23:58:56 -06:00 |
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tangxifan
|
773e6da308
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Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
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2020-03-12 22:53:17 -06:00 |
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tangxifan
|
f90dc5c296
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remove redundant XML codes
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2020-03-12 20:44:07 -06:00 |
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tangxifan
|
29450f3472
|
debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
|
8921905bec
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annotate multiple-source and multiple-sink nets from pb to lb router
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2020-03-12 19:21:13 -06:00 |
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tangxifan
|
f0b22aaa11
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Make lb router support multiple sources to be routed
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2020-03-12 13:44:14 -06:00 |
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tangxifan
|
c40675ca9d
|
minor code formatting
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2020-03-12 11:55:25 -06:00 |
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tangxifan
|
f1e8e78410
|
minor code formatting
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2020-03-12 11:47:42 -06:00 |
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tangxifan
|
689c50dff1
|
label the routing status for each sink in lb_router
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2020-03-12 11:36:31 -06:00 |
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tangxifan
|
a1f19e776e
|
Add comments to lb router and extract a private function for routing a single net
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2020-03-12 11:05:38 -06:00 |
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tangxifan
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cd50155e29
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rename variables in lb router
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2020-03-12 10:24:38 -06:00 |
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tangxifan
|
17a1c61b9d
|
minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
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tangxifan
|
8e796f152f
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add comments to lb_router about how-to-use
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2020-03-11 21:05:06 -06:00 |
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tangxifan
|
2a260a05aa
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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tangxifan
|
aff73bdd74
|
deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
|
b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
|
5558932762
|
use sorted edges in building routing modules
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2020-03-08 15:31:41 -06:00 |
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tangxifan
|
f9499afe04
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remove unused variable
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2020-03-08 15:00:01 -06:00 |
|
tangxifan
|
0c7aa2581d
|
update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
|
tangxifan
|
ca92c2717f
|
bug fix for tile directs
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2020-03-07 16:00:32 -07:00 |
|
tangxifan
|
37423729ec
|
bug fixing for naming the duplicated pins
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2020-03-07 15:44:57 -07:00 |
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tangxifan
|
5be118d695
|
tileable rr_graph builder ready to debug
|
2020-03-06 16:18:45 -07:00 |
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tangxifan
|
6e83154703
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move rr_gsb and rr_chan to tileable rr_graph builder
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2020-03-04 14:14:28 -07:00 |
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tangxifan
|
4b7d2221d1
|
adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
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tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
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tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
|
24f7416c71
|
adapt analysis SDC writer for grids
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2020-03-02 17:15:01 -07:00 |
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tangxifan
|
6474183539
|
adapt analysis SDC writer for routing modules
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2020-03-02 14:29:58 -07:00 |
|
tangxifan
|
543cff58b9
|
start porting analysis SDC writer
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2020-03-02 13:44:08 -07:00 |
|
tangxifan
|
a17c14c363
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
tangxifan
|
aa66042dfb
|
move simulation setting annotation to a separated source file
|
2020-02-29 15:19:02 -07:00 |
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tangxifan
|
7b18f7cd09
|
now the auto select number of clocks in simulation is online
|
2020-02-29 13:29:16 -07:00 |
|
tangxifan
|
3807a940f4
|
fixed critical bugs in bitstream generation and now we pass microbenchmarks
|
2020-02-28 16:45:50 -07:00 |
|
tangxifan
|
9fd184e3ab
|
rm out-of-date script
|
2020-02-28 15:42:18 -07:00 |
|
tangxifan
|
05ebd77d7d
|
start debugging with micro benchmarks. Spot problem in local routing
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2020-02-28 15:41:32 -07:00 |
|
tangxifan
|
a6c2d2c7d1
|
bug fixed for io location mapping
|
2020-02-28 14:46:01 -07:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
542fadaaae
|
allow users to use VPR critical path delay in OpenFPGA simulation
|
2020-02-28 12:10:27 -07:00 |
|
tangxifan
|
de8425874c
|
use user defined critical path delay in SDC generation
|
2020-02-28 11:24:39 -07:00 |
|
tangxifan
|
092e10afda
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
tangxifan
|
e45fa18c4c
|
adapt PnR SDC writer
|
2020-02-28 10:06:35 -07:00 |
|
tangxifan
|
89c51b70e3
|
split sdc option into two categories which will be called by different commands
|
2020-02-28 09:48:58 -07:00 |
|
tangxifan
|
fdcb982903
|
adapt pnr sdc grid writer
|
2020-02-27 21:06:33 -07:00 |
|
tangxifan
|
b4ed931ac6
|
adapt sdc routing writer
|
2020-02-27 20:35:56 -07:00 |
|
tangxifan
|
d136ac236f
|
adapt sdc memory utils
|
2020-02-27 19:39:57 -07:00 |
|
tangxifan
|
78476ca774
|
adapt sdc writer utils
|
2020-02-27 19:36:28 -07:00 |
|
tangxifan
|
8322b1623d
|
start porting SDC generator
|
2020-02-27 19:30:36 -07:00 |