Commit Graph

133 Commits

Author SHA1 Message Date
tangxifan 2c4372c506 add reserved BLB/WL port naming 2019-09-22 12:16:43 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
tangxifan d83cad7c2e refactoring Verilog generation for routing channels 2019-09-16 17:35:51 -06:00
tangxifan 29e80d157c Start developing BitstreamContext 2019-09-13 21:27:47 -06:00
tangxifan e64cfc5852 start refactoring memory decoders 2019-09-13 20:58:55 -06:00
tangxifan 009c0d63b5 refactored the memory bank. Ready to plug-in the test 2019-09-13 15:05:31 -06:00
tangxifan 99c30fa7dd keep refactoring the memory Verilog generation 2019-09-13 14:02:04 -06:00
tangxifan 2b829238b5 refactored wire Verilog generation 2019-09-12 20:49:02 -06:00
tangxifan 62853c092f refactoring local encoders. Ready to plug in 2019-09-10 15:16:29 -06:00
tangxifan e623c19055 implementing mux Verilog generation. Bugs detected, fixing ongoing 2019-09-04 23:54:53 -06:00
tangxifan 4d183a3fe4 start developing mux Verilog module generation 2019-09-03 16:59:03 -06:00
tangxifan a8c803f08f try to fix bugs in explicit port mapping 2019-09-02 16:37:43 -06:00
tangxifan fe7dfd59c3 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-24 23:54:37 -06:00
tangxifan 63f40f48fa develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-24 19:23:33 -06:00
tangxifan 27b619554d add stats for verilog modules 2019-08-23 20:23:42 -06:00
tangxifan ad06e9c98c plug in module manager 2019-08-23 20:23:41 -06:00
tangxifan 39853408dd add recursive global port searching for circuit library 2019-08-23 20:23:41 -06:00
tangxifan fcb31e4c24 add stats for verilog modules 2019-08-23 18:41:16 -06:00
tangxifan 8eebca9daa plug in module manager 2019-08-23 17:39:29 -06:00
tangxifan 37a092e885 add recursive global port searching for circuit library 2019-08-23 16:36:30 -06:00
tangxifan 931b042750 refactoring module manager 2019-08-23 12:52:01 -06:00
tangxifan 732e24767f developing module manager 2019-08-22 23:49:35 -06:00
tangxifan d8eb9866a0 refactored gate verilog generation 2019-08-21 18:49:48 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 60e8d2b29f add missing files and try to refactor submodule essential 2019-08-20 16:13:08 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan 5ece7ab6d0 start refactoring the bitstream part using spice_models 2019-08-16 15:58:14 -06:00
tangxifan 4eb046760b still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix 2019-08-15 21:57:59 -06:00
tangxifan d2d8af5416 bug fixing for pb_type num_conf_bits and num_iopads stats 2019-08-13 17:34:09 -06:00
tangxifan edfa72a666 try to fix the bug in clock net identification 2019-08-13 16:47:28 -06:00
tangxifan 392f579836 add linking functions for circuit models and architecture, memory sanitizing is ongoing 2019-08-13 13:25:23 -06:00
tangxifan c004699a14 complete parsers for ports 2019-08-09 21:00:41 -06:00
tangxifan 74da4ed51a start creating the class for circuit models 2019-08-07 11:38:45 -06:00
tangxifan b4f3dfc82d bug fixing for local encoder's bitstream generation 2019-08-06 14:17:57 -06:00
tangxifan 890ff05628 bug fixing and get ready for testing 2019-08-06 14:17:56 -06:00
tangxifan 386bddacd1 updated bitstream generator for local encoders 2019-08-06 14:17:56 -06:00
tangxifan 003883b13b implementing the local encoders 2019-08-06 14:17:55 -06:00
tangxifan fb2ca66ce9 start adding submodules of local encoders to multiplexer 2019-08-06 14:17:55 -06:00
tangxifan dcc96bf7f5 bug fixing 2019-07-17 08:25:52 -06:00
tangxifan bcc6346533 speeding up identifying unique modules in routing 2019-07-14 13:49:20 -06:00
tangxifan 4c6e245885 speed-up the unique routing process 2019-07-14 12:22:00 -06:00
tangxifan b690e702f6 adding more info to show the progress bar in backannotating GSBs 2019-07-13 19:53:44 -06:00
tangxifan aa4cd850ae try to optimize the runtime of routing uniqueness detection 2019-07-13 18:10:34 -06:00
tangxifan 78578f66c5 bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG 2019-07-13 14:48:32 -06:00
tangxifan f0ecc51b51 bug fixing to resolve the conflicts between explicit port map and standard cell map 2019-07-12 10:38:20 -06:00
tangxifan acee0161c7 Merge branch 'tileable_routing' into dev 2019-07-10 15:13:24 -06:00
tangxifan b7f9831bd2 add statistics for unique GSBs 2019-07-10 13:08:03 -06:00
tangxifan c6a4d29ed8 Merge branch 'tileable_routing' into dev 2019-07-10 12:05:43 -06:00
tangxifan edfe3144c3 update profiling, found where runtime is lost 2019-07-09 20:28:01 -06:00