Ganesh Gore
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d90329678a
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-09-14 12:11:36 -06:00 |
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Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
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Ganesh Gore
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e5c99c8b12
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Quick terminate on fail added
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2019-09-13 23:56:38 -06:00 |
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Ganesh Gore
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10eba0f78c
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Updated script.sh with new paramters
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2019-09-13 23:31:23 -06:00 |
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Ganesh Gore
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bd9e57bc37
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Added better task name
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2019-09-13 23:30:42 -06:00 |
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Ganesh Gore
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a6e592247e
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Replaced options exit_on fail and show_thread logs
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2019-09-13 22:50:20 -06:00 |
tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
Baudouin Chauviere
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1801820429
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Merge branch 'explicit_verilog' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-09-13 16:03:13 -06:00 |
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Baudouin Chauviere
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737cfb1086
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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Baudouin Chauviere
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63e6ed21b5
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Fully functional
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2019-09-13 16:02:06 -06:00 |
egiacomin
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f9f3e290c0
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Update building.md
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2019-09-13 15:59:51 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
|
b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |
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tangxifan
|
0e6c88dd52
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delete legacy codes for wire Verilog generation
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2019-09-12 21:06:53 -06:00 |
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tangxifan
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c20e182484
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plugged in the refactored wire Verilog generation
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2019-09-12 20:56:30 -06:00 |
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tangxifan
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2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
|
2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
|
0399319212
|
refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
|
0711aa1bd6
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minor bug fixing
|
2019-09-10 16:56:14 -06:00 |
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tangxifan
|
82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
|
5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
|
Ganesh Gore
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d64bb18346
|
Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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tangxifan
|
59edd49862
|
refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
|
Ganesh Gore
|
d55b7e9497
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-06 11:49:38 -04:00 |
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Ganesh Gore
|
bcbcd463fe
|
Added pending runs in log
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2019-09-06 11:48:13 -04:00 |
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tangxifan
|
86413a33c2
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Merge branch 'dev' into refactoring
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2019-09-05 17:09:04 -06:00 |
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tangxifan
|
bc9d95408e
|
bug fixed and refactored intermediate buffer addition
|
2019-09-05 16:09:28 -06:00 |
|
Ganesh Gore
|
9abc1e1e7d
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-05 13:12:41 -04:00 |
|
Ganesh Gore
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702a7683a8
|
Ensure strict exit of fpga_flow on error
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2019-09-05 10:23:35 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
|
fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
|
b6bb433edc
|
bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
|
4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
|
Ganesh Gore
|
f862ac02c8
|
Restored OSX header installation [ci skip]
|
2019-09-03 11:05:42 -06:00 |
|
Ganesh Gore
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37439578db
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Removed OSX package installer to test
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2019-09-03 10:32:14 -06:00 |
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tangxifan
|
a8c803f08f
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try to fix bugs in explicit port mapping
|
2019-09-02 16:37:43 -06:00 |
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tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
|
4490c78195
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-09-02 14:30:55 -06:00 |
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tangxifan
|
395bf4fbdf
|
refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
|
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
e37ac1a565
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-02 00:19:19 -06:00 |