tangxifan
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50f7d1eae3
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bug fixing in Verilog port merging and instanciation
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2019-10-11 14:20:04 -06:00 |
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tangxifan
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663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
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c9950162d1
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start plug in new Verilog writer. Start debugging
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2019-10-10 22:02:46 -06:00 |
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tangxifan
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1f650aac73
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add local direct connection Verilog code generation
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2019-10-10 20:54:31 -06:00 |
Tim Ansell
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916cfa27ed
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Small formatting fixes to the README
* Make the compile steps easy to copy.
* Small wording fixes.
* Use relative links (github rewrites them).
* Remove unneeded `<br>` tags.
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2019-10-10 19:39:44 -07:00 |
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tangxifan
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f2b3341d87
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
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tangxifan
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e5956467fd
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developing verilog writer for modules
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2019-10-10 14:43:32 -06:00 |
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tangxifan
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edad988ebb
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add net accessor and mutators to module manager
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2019-10-09 21:14:30 -06:00 |
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tangxifan
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557d8b60f3
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start implementing module graph-based connection
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2019-10-09 20:30:16 -06:00 |
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tangxifan
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9cb6e64ab3
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refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
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tangxifan
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6f42aac626
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add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
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tangxifan
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6bed89c237
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refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
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tangxifan
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ea2942640e
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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tangxifan
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512e9f4e8e
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refactoring Verilog generation for primitive pb_types
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2019-10-08 12:10:26 -06:00 |
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tangxifan
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173b886314
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add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |
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tangxifan
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86c9af872e
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refactoring physical block Verilog generation
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2019-10-07 17:39:00 -06:00 |
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tangxifan
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997bfdbb95
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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tangxifan
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3ca6f08aa4
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start refactoring physical block Verilog generation
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2019-10-06 19:27:55 -06:00 |
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tangxifan
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1e183e7885
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refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
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tangxifan
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393f0b0ac3
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align formal verification port inside refactored routing blocks
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2019-10-05 21:16:48 -06:00 |
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tangxifan
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86387ff79c
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Merge branch 'refactoring' into dev
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2019-10-05 18:15:31 -06:00 |
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tangxifan
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c920047ee8
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refactored Verilog generation for connection blocks
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2019-10-05 18:14:23 -06:00 |
AurelienUoU
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0983f85684
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-10-05 12:46:34 -06:00 |
Baudouin Chauviere
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027272c976
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Faster regression test
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2019-10-05 12:10:55 -06:00 |
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tangxifan
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2d7e8d9811
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add check codes for memory buses
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2019-10-05 11:07:26 -06:00 |
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tangxifan
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6b301d9f44
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Merge branch 'dev' into refactoring
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2019-10-04 22:47:29 -06:00 |
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tangxifan
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b905c0c68c
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refactored memory module Verilog generation for scan-chains
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2019-10-04 22:45:45 -06:00 |
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AurelienUoU
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7aa24f407e
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Fix explicit port name in CBs
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2019-10-04 11:20:46 -06:00 |
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Baudouin Chauviere
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6f7023658e
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Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
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2019-10-03 14:59:04 -06:00 |
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Baudouin Chauviere
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95596bb4f8
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Correction on the cb vs sb corrdinator. Does not fix the problem though
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2019-10-03 13:50:01 -06:00 |
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Baudouin Chauviere
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db059af8b8
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Lighten the regression test
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2019-10-03 13:33:28 -06:00 |
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Baudouin Chauviere
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c7e1f7d90b
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Added explicit_verilog to regression test in a clean way
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2019-10-03 10:17:04 -06:00 |
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Baudouin Chauviere
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01ff484158
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Explicit verilog passing all tests
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2019-10-02 10:22:28 -06:00 |
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Baudouin Chauviere
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6b3e1fd410
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Get backup verilog_routing.c
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2019-10-02 08:54:56 -06:00 |
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Baudouin Chauviere
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829cbcfbe3
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Merge
Merge remote-tracking branch 'origin' into explicit_verilog
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2019-10-01 16:54:27 -06:00 |
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Baudouin Chauviere
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33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
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Baudouin Chauviere
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7c3ab38410
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Hot fix
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2019-10-01 16:40:16 -06:00 |
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Baudouin Chauviere
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633a12ee08
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Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
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AurelienUoU
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36f7624b95
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Point to point truth table typo fix
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2019-10-01 13:07:27 -06:00 |
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AurelienUoU
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e2867019e1
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Typo fixing
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2019-09-30 10:38:02 -06:00 |
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AurelienUoU
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74f7a3cfb2
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Doc fixing
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2019-09-30 10:29:42 -06:00 |
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AurelienUoU
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fdc3c5e4a9
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-30 10:02:11 -06:00 |
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AurelienUoU
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5ac79f4805
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Point to point documentation
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2019-09-30 10:00:46 -06:00 |
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tangxifan
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b082e60c10
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start refactoring instanciation of memory modules
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2019-09-29 18:20:56 -06:00 |
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tangxifan
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3726e691f4
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simplify the local wire generation for ccffs
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2019-09-28 21:36:56 -06:00 |
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tangxifan
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1983e56557
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make local configuration bus generation more general
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2019-09-28 21:02:14 -06:00 |
Ganesh Gore
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069f628bb0
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Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
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2019-09-28 11:21:37 -06:00 |
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tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
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f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |