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OpenFPGA
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Merge branch 'dev' into refactoring

This commit is contained in:
tangxifan 2019-09-05 17:09:04 -06:00
parent bc9d95408e 9abc1e1e7d
commit 86413a33c2
5 changed files with 70 additions and 35 deletions
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7
docs/source/conf.py
View File

@ -19,7 +19,7 @@ import shlex
import sphinx_rtd_theme
# Uncomment for local build
# Uncomment for local build
#html_theme = "sphinx_rtd_theme"
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
@ -55,7 +55,8 @@ extensions = [
'sphinx.ext.todo',
'sphinx.ext.mathjax',
'sphinx.ext.graphviz',
'sphinxcontrib.bibtex'
'sphinxcontrib.bibtex',
'sphinx.ext.autosectionlabel',
]
# Add any paths that contain templates here, relative to this directory.
@ -89,7 +90,7 @@ pygments_style = 'sphinx'
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True
#Number figures for referencing
# Number figures for referencing
numfig = True

2
docs/source/run_fpga_flow.rst
View File

@ -114,7 +114,7 @@ General Arguments
.. option:: --debug
To enable detail logs printing.
To enable detailed log printing.
.. option:: --flow_config

89
docs/source/run_fpga_task.rst
View File

@ -4,17 +4,17 @@ OpenFPGA Task
---------------
Tasks provide a framework for running the :ref:`run_fpga_flow` on
multiple benchmarks, architectures and set of OpenFPGA parameters.
multiple benchmarks, architectures, and set of OpenFPGA parameters.
The structure of the framework is very similar to
`VTR-Tasks <https://docs.verilogtorouting.org/en/latest/vtr/tasks/>`_
implementation with additional functionality and minor file extention changes.
implementation with additional functionality and minor file extension changes.
Task Directory
~~~~~~~~~~~~~~
The tasks are store in a ``TASK_DIRECTORY``, which by default points to
The tasks are stored in a ``TASK_DIRECTORY``, which by default points to
``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in
task directory consisting of ``../config/task.conf`` file can be reffered as a
task directory consisting of ``../config/task.conf`` file can be referred to as a
task.
To create as task name called ``basic_flow`` following directory has to exist::
@ -31,22 +31,55 @@ Running OpenFPGA Task:
At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
open_fpga_flow.py <task1_name> <task2_name> ...
open_fpga_flow.py <task1_name> <task2_name> ... [<options>]
where:
* ``<task_name>`` is the name of the task to run
* ``<options>`` Other command line arguments described below
Craeating A New OpenFPGA Task:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Create the folder ``${TASK_DIRECTORY}/<task_name>`` and create a file called
``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it.
Command-line Options
~~~~~~~~~~~~~~~~~~~~
.. option:: --maxthreads <number_of_threads>
This option defines the number of threads to run while executing task.
Each combination of architecture, benchmark and set of OpenFPGA Flow options
runs in a individual thread.
.. option:: --skip_thread_logs
Passsing this option skips printing logs from each OpenFPGA Flow script run.
.. option:: --exit_on_fail
Passsing this option exits the OpenFPGA task script with returncode 1,
if any threads fail to execute successfully. It is mainly used to while
performing regression test.
.. option:: --test_run
This option allows to debug OpenFPGA Task script
by skiping actual execution of OpenFPGA flow .
Passing this option prints the list of
commnad generated to execute using OpenFPGA flow.
.. option:: --debug
To enable detailed log printing.
Creating a new OpenFPGA Task
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Configuring a New Task
~~~~~~~~~~~~~~~~~~~~~~
- Create the folder ``${TASK_DIRECTORY}/<task_name>``
- Create a file ``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it
- Configure the task as explained in :ref:`Configuring a new OpenFPGA Task`
Configuring a new OpenFPGA Task
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The task configuration file ``task.conf`` consists of ``GENERAL``,
``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and
@ -54,16 +87,16 @@ The task configuration file ``task.conf`` consists of ``GENERAL``,
Declaring all the above sections are mandatory.
.. note::
Configuration file supports all the OpenFPGA Variables refer
:ref:`openfpga-variables` section to know more. Variables in configuration
file is declares as ``${PATH:<variable_name>}``
The configuration file supports all the OpenFPGA Variables refer
:ref:`openfpga-variables` section to know more. Variable in the configuration
file is declared as ``${PATH:<variable_name>}``
General Section
^^^^^^^^^^^^^^^
.. option:: fpga_flow==<yosys_vpr|vpr_blif>
Defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
.. option:: power_analysis=<true|false>
@ -71,7 +104,7 @@ General Section
.. option:: power_tech_file=<path_to_tech_XML_file>
Declares which tech XML file to be used while perforing Power Analysis.
Declares which tech XML file to use while performing Power Analysis.
.. option:: spice_output=<true|false>
@ -85,14 +118,13 @@ General Section
.. option:: timeout_each_job=<true|false>
Specifies the the timeout for each :ref:`run_fpga_flow` execution. Default
is set to ``20 min``
Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. ``
Architectures Sections
^^^^^^^^^^^^^^^^^^^^^^
User can define the list of architecure files in this section.
User can define the list of architecture files in this section.
.. option:: arch<arch_label>=<xml_architecture_file_path>
@ -102,7 +134,7 @@ Architectures Sections
.. note::
In final OpenFPGA Task result the architecture will be referred by its
In the final OpenFPGA Task result, the architecture will be referred by its
``arch_label``.
Benchmarks Sections
@ -117,7 +149,7 @@ Benchmarks Sections
architecture file
For Example following code shows how to define a benchmarks,
with single file multiple files and files added from specific directory.
with a single file, multiple files and files added from a specific directory.
.. code-block:: text
@ -133,17 +165,17 @@ Benchmarks Sections
.. note::
``bench_label`` is referred again in ``Synthesis_Param`` section to
provide addional information about benchmark
provide additional information about benchmark
Synthesis Parameter Sections
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
User can define extra parameters for each benchmark defined in the
User can define extra parameters for each benchmark in the
``BENCHMARKS`` sections.
.. option:: bench<bench_label>_top=<Top_Module_Name>
This defines the Top Level module name for ``bench_label`` benchmark.
By default, the top level module name is cosidereed as a ``top``.
This option defines the Top Level module name for ``bench_label`` benchmark.
By default, the top-level module name is considered as a ``top``.
.. option:: bench<bench_label>_yosys_tmpl=<yosys_template_file>
@ -163,13 +195,13 @@ Synthesis Parameter Sections
.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
In case of running ``blif_vpr_flow`` with verification this option provides
the source verilog design for ``bench_label`` benchmark to be used
the source Verilog design for ``bench_label`` benchmark to be used
while verification.
Script Parameter Sections
^^^^^^^^^^^^^^^^^^^^^^^^^
The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
The section is referred with ``parameter_set_label`` in final result file.
The section is referred with ``parameter_set_label`` in the final result file.
For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments.
@ -184,7 +216,7 @@ For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fi
fix_route_chan_width=50
Example Task Configuration File
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: text
[GENERAL]
@ -210,4 +242,3 @@ Example Task Configuration File
[SCRIPT_PARAM_Slack_80]
min_route_chan_width=1.8

3
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -452,6 +452,7 @@ def run_yosys_with_abc():
if process.returncode:
logger.info("Yosys failed with returncode %d",
process.returncode)
raise subprocess.CalledProcessError(0, command)
except:
logger.exception("Failed to run yosys")
clean_up_and_exit("")
@ -522,6 +523,7 @@ def run_ace2():
if process.returncode:
logger.info("ACE2 failed with returncode %d",
process.returncode)
raise subprocess.CalledProcessError(0, command)
except:
logger.exception("Failed to run ACE2")
clean_up_and_exit("")
@ -771,6 +773,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
if process.returncode:
logger.info("Standard VPR run failed with returncode %d",
process.returncode)
raise subprocess.CalledProcessError(0, command)
except (Exception, subprocess.CalledProcessError) as e:
logger.exception("Failed to run VPR")
filter_failed_process_output(e.output)

4
openfpga_flow/scripts/run_fpga_task.py
View File

@ -55,7 +55,7 @@ parser.add_argument('--debug', action="store_true",
help="Run script in debug mode")
parser.add_argument('--exit_on_fail', action="store_true",
help="Exit script with return code")
parser.add_argument('--skip_tread_logs', action="store_true",
parser.add_argument('--skip_thread_logs', action="store_true",
help="Skips logs from running thread")
args = parser.parse_args()
@ -364,7 +364,7 @@ def run_single_script(s, eachJob):
stderr=subprocess.STDOUT,
universal_newlines=True)
for line in process.stdout:
if not args.skip_tread_logs:
if not args.skip_thread_logs:
strip_child_logger_info(line[:-1])
sys.stdout.buffer.flush()
output.write(line)