AurelienUoU
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a35e2936b2
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Fix verilog generation for direct connexion from directlist
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2019-09-25 16:44:00 -06:00 |
tangxifan
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2b0e2615fa
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refactored sram port addition to module manager
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2019-09-25 16:09:58 -06:00 |
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tangxifan
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c911f15a67
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add formal verification port to SB Verilog generation
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2019-09-23 21:15:45 -06:00 |
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tangxifan
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e1742b68ef
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add pre-processing flag support for module manager
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2019-09-23 20:25:53 -06:00 |
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AurelienUoU
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feddcbcb21
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-23 11:41:38 -06:00 |
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tangxifan
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d2ddbc19a3
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refactoring the reserved sram port generation
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2019-09-22 16:38:16 -06:00 |
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tangxifan
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8b3de892ef
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simplify the regression test commands
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2019-09-22 12:18:44 -06:00 |
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tangxifan
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2c4372c506
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add reserved BLB/WL port naming
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2019-09-22 12:16:43 -06:00 |
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tangxifan
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1e4177067d
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remove port size in the module definition
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2019-09-22 11:21:43 -06:00 |
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tangxifan
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5efea159c5
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Simplify part of regression test to min_route_chan_width
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2019-09-22 11:14:33 -06:00 |
Ganesh Gore
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1dffe54807
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-22 00:21:25 -06:00 |
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Ganesh Gore
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50039a4b6e
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Added remove run directory option
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2019-09-21 23:35:56 -06:00 |
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AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
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tangxifan
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0ff0c8cf06
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bug fix for IO=1
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2019-09-19 15:43:25 -06:00 |
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tangxifan
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4e7af5cdc5
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update tileable_routing test
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2019-09-18 15:59:32 -06:00 |
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tangxifan
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e0b253d30a
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minor fix for non-LUT intermedate buffer case
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2019-09-18 15:15:03 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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Ganesh Gore
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8afcba2c45
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-18 12:15:42 -06:00 |
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Ganesh Gore
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cd5fd6ce6c
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Added explicit checking to VVP execution
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2019-09-18 12:14:26 -06:00 |
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Ganesh Gore
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56c40ca06d
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-17 22:12:11 -06:00 |
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Ganesh Gore
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169732ccc1
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Added verbose option in VVP output
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2019-09-17 22:09:37 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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Ganesh Gore
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7be83235a0
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-16 21:25:26 -06:00 |
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Ganesh Gore
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678e3181ba
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Made compact_routing_hierarchy options uncond
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2019-09-16 21:22:13 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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2294aecef2
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remove old codes and compact new codes
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2019-09-16 20:19:14 -06:00 |
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tangxifan
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c5ee81541a
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remove dead codes in routing module generation
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2019-09-16 18:47:01 -06:00 |
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tangxifan
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0963852091
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remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
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2019-09-16 18:38:37 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
Baudouin Chauviere
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d5ebe66ad9
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Bug fix
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2019-09-16 10:57:52 -06:00 |
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Ganesh Gore
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81b9c5b266
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Added flag for VVP exit code
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2019-09-14 12:35:47 -06:00 |
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Ganesh Gore
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d90329678a
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-09-14 12:11:36 -06:00 |
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Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
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Ganesh Gore
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e5c99c8b12
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Quick terminate on fail added
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2019-09-13 23:56:38 -06:00 |
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Ganesh Gore
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10eba0f78c
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Updated script.sh with new paramters
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2019-09-13 23:31:23 -06:00 |
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Ganesh Gore
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bd9e57bc37
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Added better task name
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2019-09-13 23:30:42 -06:00 |
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Ganesh Gore
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a6e592247e
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Replaced options exit_on fail and show_thread logs
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2019-09-13 22:50:20 -06:00 |
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tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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Baudouin Chauviere
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1801820429
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Merge branch 'explicit_verilog' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-09-13 16:03:13 -06:00 |
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Baudouin Chauviere
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737cfb1086
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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Baudouin Chauviere
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63e6ed21b5
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Fully functional
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2019-09-13 16:02:06 -06:00 |
egiacomin
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f9f3e290c0
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Update building.md
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2019-09-13 15:59:51 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
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b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |