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OpenFPGA
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658 Commits

Author SHA1 Message Date
egiacomin 77e1480a4c
Merge pull request #14 from LNIS-Projects/dev 
Dev - Critical bug fixing and add support for MUX2 standard cell mapping
 2019-07-17 11:55:52 -06:00
tangxifan 32e3a556b9 bug fixing herited from explicit mapping 2019-07-17 09:26:05 -06:00
tangxifan 8b8e18a8de bug fixing for mux subckt names 2019-07-17 08:59:57 -06:00
tangxifan a2505ff16a turn on std cell explicit port map 2019-07-17 08:36:09 -06:00
tangxifan dcc96bf7f5 bug fixing 2019-07-17 08:25:52 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
tangxifan 4672311aae
Merge pull request #13 from LNIS-Projects/dev 
Dev
 2019-07-16 22:10:04 -04:00
AurelienAlacchi 3aa0a4a5e6
Merge pull request #12 from LNIS-Projects/tangxifan-patch-1 
Update building.md
 2019-07-16 21:20:38 -04:00
tangxifan d6dfc29508 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
tangxifan 61026dc623
Update building.md 2019-07-16 16:58:11 -04:00
tangxifan 954a8c14f7 remove redundant files 2019-07-16 14:55:04 -06:00
tangxifan da8745b163
Update README.md 2019-07-16 16:51:52 -04:00
tangxifan 0c68642aad
Update README.md 2019-07-16 16:49:15 -04:00
tangxifan e9154b1f74 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 14:42:45 -06:00
tangxifan b807fdb38a Merge branch 'tileable_routing' into dev 2019-07-16 14:38:18 -06:00
tangxifan be255edc68 now use vtr_assert in ace 2019-07-16 14:37:19 -06:00
Baudouin Chauviere 712eccfa30 Merge branch 'dev', remote-tracking branch 'origin' into explicit_verilog 2019-07-16 13:37:52 -06:00
Baudouin Chauviere 65122d04b3 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 13:37:21 -06:00
tangxifan 115411941b Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 13:15:45 -06:00
AurelienUoU 509c1d2c80 Link path correction 2019-07-16 13:13:58 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
AurelienAlacchi b0017cdbdf
Merge pull request #11 from LNIS-Projects/dev 
Dev
 2019-07-16 13:08:24 -06:00
Baudouin Chauviere e602006a07 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-16 12:45:13 -06:00
AurelienUoU fe218fc207 Tutorial update 2019-07-16 11:52:24 -06:00
AurelienUoU a04555419a Typo fix 2019-07-16 07:30:25 -06:00
AurelienUoU 3d079c9421 Add folder creation in tuto_fpga_flow.sh to ease the use 2019-07-16 07:20:21 -06:00
AurelienUoU b810b5cab9 fpga_flow bug fix + upload k8 architecture 2019-07-16 07:04:45 -06:00
AurelienUoU 35e1962732 Merge branch 'dev' into documentation 2019-07-15 21:19:26 -06:00
AurelienUoU 1cf4e78502 Update documentation and help 2019-07-15 21:16:15 -06:00
tangxifan bcc6346533 speeding up identifying unique modules in routing 2019-07-14 13:49:20 -06:00
tangxifan 4c6e245885 speed-up the unique routing process 2019-07-14 12:22:00 -06:00
tangxifan b690e702f6 adding more info to show the progress bar in backannotating GSBs 2019-07-13 19:53:44 -06:00
tangxifan aa4cd850ae try to optimize the runtime of routing uniqueness detection 2019-07-13 18:10:34 -06:00
tangxifan 78578f66c5 bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG 2019-07-13 14:48:32 -06:00
AurelienUoU 1a5c5ff4a6 Update demo simulation result path 2019-07-12 16:52:54 -06:00
AurelienUoU 19ccbce9d0 Rename option to use circuit_model rather than spice_model 2019-07-12 16:18:28 -06:00
AurelienUoU d10cc34c9e Update Readme and tutorial 2019-07-12 14:56:08 -06:00
Baudouin Chauviere f140e08093 Pre-Merge modifications 2019-07-12 10:48:43 -06:00
Baudouin Chauviere a0f1f8d163 Fix when explicit verilog is NOT used 2019-07-12 10:39:31 -06:00
tangxifan f0ecc51b51 bug fixing to resolve the conflicts between explicit port map and standard cell map 2019-07-12 10:38:20 -06:00
AurelienUoU e65cf9f5fd Update ERI-demo 2019-07-12 08:55:19 -06:00
Baudouin Chauviere 40d3460bac Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-11 22:13:30 -06:00
Baudouin Chauviere 29ffa1cdcb Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-11 22:13:09 -06:00
Baudouin Chauviere e461cd0b99 Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-11 22:09:49 -06:00
Baudouin Chauviere 1431ee2f82 Fix Explicit verilog 2019-07-11 22:09:34 -06:00
tangxifan cffdebd912 bug fixed for the tileable RR graph generator for heterogeneous blocks 2019-07-11 21:02:09 -06:00
tangxifan 75ff2e904e Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-11 19:41:24 -06:00
tangxifan e633e3d17b update fpga_flow scripts to support vpr_only flow 2019-07-11 19:40:58 -06:00
Baudouin Chauviere c9b84f61c9 Hot fix 2019-07-11 17:39:02 -06:00
Baudouin Chauviere d0cd5a2bc1 Hot fix 2019-07-11 17:27:31 -06:00