021fedbc12
update fabric key to synchronize with new module/instance naming
2020-07-24 12:55:40 -06:00
fefcd88f14
update openfpga architecture README for power-gating
2020-07-22 21:55:59 -06:00
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
ca867ea6fa
add power gate inverter test case (full testbench)
2020-07-22 20:09:52 -06:00
87ef7f9f99
add power gate example architecture
2020-07-22 20:06:10 -06:00
8ade40713a
add missing architecture for CI
2020-07-22 14:07:39 -06:00
1a1c3885e7
use k6 n10 in mux designs to speed up CI
2020-07-22 13:54:09 -06:00
95c1fe61e1
use k6 n8 in mux design to speed up CI
2020-07-22 13:49:03 -06:00
f754c8af06
use k6_n10 architecture to reduce CI runtime
2020-07-22 13:45:55 -06:00
92c3449999
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
05dccadf21
bug fix in the testcases using yosys_vpr flow
2020-07-22 12:44:19 -06:00
7d39e136a4
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
1d36de817f
adapt generate bitstream testcase to use yosys vpr flow
2020-07-22 12:24:34 -06:00
b96cdbf857
adapt preconfig test cases to use yosys_vpr flow
2020-07-22 12:23:39 -06:00
d8804f4ec1
deploy yosys_vpr flow to basic regression tests
2020-07-22 12:21:59 -06:00
f4e77e3bad
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-22 12:09:34 -06:00
3b6cd885f3
BugFix: Fixed yosys_vpr with openFPGA_Shell
2020-07-22 11:57:04 -06:00
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
ca90f337a7
add fast configuration chain test case
2020-07-15 11:56:47 -06:00
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
1e6955aaa4
rename arch directory to be clear for its usage
2020-07-04 19:13:28 -06:00
f9a2bb0490
Reorganize task directory
2020-07-04 19:06:41 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
1c634e4600
add missing task file for generate bitstream test case
2020-07-02 17:24:51 -06:00
adea6fcec4
add bitstream generation only test case to CI
2020-07-02 16:31:22 -06:00
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
20cf4acda0
add readme for architecture file naming
2020-07-01 09:54:13 -06:00
b2fb5f760c
update sample key
2020-06-27 15:01:12 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
3d56cd3060
fine tuning on the script for MCNC benchmarks
2020-06-15 20:09:46 -06:00
0d81f60fd8
add new options to openfpga task configuration files
2020-06-12 19:48:39 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
2d35848cfa
add external key test cases
2020-06-12 13:11:21 -06:00
65b387a589
develop test cases for fabric keys
2020-06-12 11:32:52 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
068d9943e7
update all the templates and regression test cases with simulation settings
2020-06-11 19:31:16 -06:00
1842bf51e1
deploy read_openfpga_simulation_setting in CI on a single test case
2020-06-11 19:31:16 -06:00
cb09896f23
add example simulation setting for openfpga flow
2020-06-11 19:31:15 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
c87dbc4880
start using counter benchmark in regression tests
2020-06-11 19:31:15 -06:00
f73dfa2bcc
bug fixed in k6_n10_40 architecture
2020-06-11 19:31:15 -06:00
baa2c6b7ef
update arch to support reset signal for SRAm
2020-06-11 19:31:14 -06:00
aac2e8c805
update openfpga architecture for memory bank usage
2020-06-11 19:31:14 -06:00
82b04ae3f0
add SRAM verilog for memory bank usage
2020-06-11 19:31:14 -06:00
3f9afea3e8
add preconfig testbench test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
288294c23a
add fast configuration test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
tangxifan
ganeshgore