Lin
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701a7a5c52
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add test case
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2024-08-26 02:45:57 -07:00 |
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Lin
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88fa9f8d39
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add test case
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2024-08-25 23:41:19 -07:00 |
tangxifan
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2c35840457
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[test] add a new test to validate CHANY clock spin in DEC
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2024-08-15 14:24:31 -07:00 |
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tangxifan
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586dd1a510
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[test] add a new and strong test to validate the disable unused clock spines
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2024-08-15 10:24:58 -07:00 |
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tangxifan
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84cc7090ce
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[test] add a new test to validate that pb pin fixup impacts global net now
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2024-08-14 10:37:46 -07:00 |
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tangxifan
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c6246ae905
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[test] typo
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2024-08-09 17:10:51 -07:00 |
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tangxifan
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38f1bdba4e
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[test] add a new test case
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2024-08-09 17:04:10 -07:00 |
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tangxifan
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57adf97fd4
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[test] fixed some bugs in clock arch
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2024-08-02 18:34:59 -07:00 |
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tangxifan
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91c4336a4a
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[test] add a new testcase to validate 3-layer clock architecture
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2024-08-02 18:18:49 -07:00 |
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tangxifan
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84c2b27c7b
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[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
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2024-08-02 17:24:44 -07:00 |
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tangxifan
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3181f2d5a3
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[test] add a new test to validate multiple entry points for a clock network
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2024-07-30 14:17:14 -07:00 |
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tangxifan
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687f03fd77
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[test] add a new test to validate clock network on module named by index
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2024-07-30 14:06:53 -07:00 |
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tangxifan
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f9f9aab7d9
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[test] typo
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2024-07-30 12:50:14 -07:00 |
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tangxifan
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ad275fba44
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[test] add a new test to validate clock network entry point on a y-direction cb
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2024-07-30 12:48:35 -07:00 |
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tangxifan
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e614ca7380
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[test] use new syntax
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2024-07-10 15:03:27 -07:00 |
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tangxifan
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977283dd34
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[core] typo
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2024-07-10 14:12:49 -07:00 |
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tangxifan
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af996e563e
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[test] add a new test to validate reset generated by internal driver through programmable clock network
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2024-07-10 14:11:06 -07:00 |
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tangxifan
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b6ff69faac
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[test] reworking the testcase to validate clock network with internal drivers
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2024-07-10 11:36:22 -07:00 |
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tangxifan
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dbe8e63f53
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[test] remove unused files
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2024-07-10 10:15:47 -07:00 |
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tangxifan
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77304164f4
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[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
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2024-07-10 10:13:41 -07:00 |
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tangxifan
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191a3d1c5e
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[test] update W
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2024-07-10 10:01:31 -07:00 |
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tangxifan
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81fe722d98
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[test] adjust W
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2024-07-09 23:49:01 -07:00 |
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tangxifan
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43dbeafd44
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[test] typo
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2024-07-09 20:27:28 -07:00 |
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tangxifan
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9ce4b57363
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[test] typo
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2024-07-09 20:25:39 -07:00 |
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tangxifan
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e5d146a67a
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[test] add new tests to validate rst on lut and clk on lut features
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2024-07-09 20:24:23 -07:00 |
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tangxifan
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5efc9d0e00
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[test] update golden outputs
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2024-07-08 23:24:16 -07:00 |
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tangxifan
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5cb104a5f6
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[test] fixed a bug
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2024-07-08 22:04:40 -07:00 |
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tangxifan
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c30eafac9f
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[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
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2024-07-08 15:26:16 -07:00 |
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tangxifan
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b50acacfba
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[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
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2024-07-08 15:09:31 -07:00 |
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tangxifan
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6492d43a01
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[test] add a new test to validate perimeter cb using global tile clock
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2024-07-08 11:29:20 -07:00 |
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tangxifan
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5c9c4d93c5
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[core] typo
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2024-07-08 10:46:47 -07:00 |
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tangxifan
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ff56139a53
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[test] debugging
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2024-07-07 23:07:51 -07:00 |
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tangxifan
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1a5e2392fc
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[test] add a new testcase to validate clock network when perimeter cb is on
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2024-07-07 22:32:13 -07:00 |
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tangxifan
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db12532eb8
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[test] typo
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2024-07-07 21:41:39 -07:00 |
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tangxifan
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439de61fd0
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[test] fixed a bug on ecb support
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2024-07-07 14:00:11 -07:00 |
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tangxifan
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a46820b7c1
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[core] add a new test for bottom-left tile grouping
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2024-07-05 18:00:37 -07:00 |
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tangxifan
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a78fddc3cb
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[test] add a new testcase to validate perimeter cb
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2024-07-03 19:59:24 -07:00 |
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tangxifan
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7e461b09f8
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[core] add missing file
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2024-07-02 13:22:41 -07:00 |
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tangxifan
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29452a7442
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[test] fixed a bug on out-of-date arch
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2024-07-02 11:52:19 -07:00 |
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tangxifan
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e00312d29e
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[test] typo
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2024-07-01 20:34:37 -07:00 |
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tangxifan
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1bfcf7574c
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[test] validate region and single syntax
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2024-07-01 20:33:28 -07:00 |
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tangxifan
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28e3cb799e
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[test] update 2-clock arch and pcf
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2024-06-29 17:40:20 -07:00 |
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tangxifan
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12c9686c27
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[test] fixed some bugs on arch
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2024-06-29 17:38:34 -07:00 |
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tangxifan
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5dd0549aed
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[core] typo
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2024-06-29 17:17:54 -07:00 |
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tangxifan
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bc2f02866d
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[test] update testcase for 2-clk on programmable clock network
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2024-06-29 17:17:05 -07:00 |
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tangxifan
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286df30947
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[test] update clock arch xml syntax
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2024-06-29 11:02:17 -07:00 |
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tangxifan
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67554cb8d8
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[test] now use correct pcf for clock network testcases
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2024-06-29 10:04:03 -07:00 |
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tangxifan
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8bc37080fa
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[core] debuggging
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2024-06-28 23:06:21 -07:00 |
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tangxifan
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1c69365938
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[core] debugging
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2024-06-28 18:17:38 -07:00 |
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tangxifan
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f1a4304ee7
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[test] add new testcases for validate clock tree disable functions
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2024-06-28 13:43:53 -07:00 |