Ganesh Gore
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5d3708651e
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Added fpga_flow and fpga_task script
+ Missed local intermediate commits
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2019-08-15 14:39:58 -06:00 |
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Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |
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Ganesh Gore
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0cc439f76c
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Working lattice benchmark unclean commit
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2019-08-08 18:08:39 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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Ganesh Gore
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3c36a51011
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Added 'rewrite_path_in_file' back to repository
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2019-07-03 12:49:25 -06:00 |
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Ganesh Gore
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53486b8a89
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Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
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2019-07-03 12:30:56 -06:00 |
tangxifan
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570f9495e6
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Merge branch 'tileable_routing' into dev
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2019-07-03 12:13:48 -06:00 |
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tangxifan
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0c3e8bb70a
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add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
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tangxifan
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ea7e119313
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Merge branch 'tileable_routing' into dev
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2019-07-03 10:37:27 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
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2019-07-03 10:33:02 -06:00 |
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tangxifan
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547c479d84
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Merge branch 'tileable_routing' into dev
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2019-07-02 16:26:51 -06:00 |
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tangxifan
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4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
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2019-07-02 15:34:59 -06:00 |
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tangxifan
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3e2a4917f5
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Merge branch 'tileable_routing' into dev
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2019-07-02 10:37:25 -06:00 |
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tangxifan
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95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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e2b7636229
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Merge pull request #6 from LNIS-Projects/multimode_clb
Multimode clb
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2019-07-02 09:48:24 -06:00 |
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tangxifan
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44301bfd77
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updated SPICE generator to avoid issues on clb2clb_direct
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2019-07-02 09:01:52 -06:00 |
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tangxifan
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5b25bbb120
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bug fixed for direct connection in CBs and direct connection in top netlist
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2019-07-01 17:25:00 -06:00 |
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Ganesh Gore
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54f6ca2687
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Added lattice benchmark settings
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2019-07-01 11:07:23 -06:00 |
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tangxifan
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c54f3905d5
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fixed broken fpga flow
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2019-06-28 13:07:04 -06:00 |
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tangxifan
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1332ba62e8
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update tileable rr_graph generator to improve routability and also enable assoicated testing
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2019-06-27 17:52:25 -06:00 |
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tangxifan
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15c536e9b4
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minor fixing in printing the rr_node stats
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2019-06-27 16:34:21 -06:00 |
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Ganesh Gore
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11e6350214
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Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev
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2019-06-27 14:22:40 -06:00 |
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tangxifan
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8edd85c9fc
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keep fixing bugs in verilog SDC generator for tileable CBs
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2019-06-26 22:58:52 -06:00 |
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tangxifan
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711e369fe7
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fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
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0fe54d87d5
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fixed a bug in SDC generator for constraining SBs in tileable arch
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2019-06-26 17:06:14 -06:00 |
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tangxifan
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7d85eb544d
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start fixing bugs for SDC generator when using tileable arch
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2019-06-26 16:48:17 -06:00 |
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tangxifan
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f5920c7422
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fix bugs in ptc_num using for SB
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2019-06-26 16:21:02 -06:00 |
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tangxifan
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3d8200e217
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critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
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d2ed82d14d
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 15:00:39 -06:00 |
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tangxifan
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57616361c2
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fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
Baudouin Chauviere
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d2bd2be76b
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Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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tangxifan
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42f85004b6
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
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9b6a4b39bb
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 11:36:08 -06:00 |
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tangxifan
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c879e7f6c5
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
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Baudouin Chauviere
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b7c2954b91
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-26 10:51:55 -06:00 |
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Baudouin Chauviere
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8f21a3b177
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Memory leakage correction
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2019-06-26 10:50:38 -06:00 |
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tangxifan
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d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
AurelienUoU
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ec504049ef
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
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tangxifan
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a3670bb752
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-26 09:45:04 -06:00 |
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Baudouin Chauviere
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56557b94e7
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Bug Fix
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2019-06-26 08:53:46 -06:00 |
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tangxifan
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3c0ef2067d
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fixed critical bugs in pass_tracks identification and update regression test for tileable arch
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2019-06-25 21:59:38 -06:00 |
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Baudouin Chauviere
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bb250ddef9
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Bug fix in cpp
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2019-06-25 16:47:10 -06:00 |
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Ganesh Gore
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6d3066174b
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Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev
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2019-06-25 15:12:13 -06:00 |
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tangxifan
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4d3b5f12b4
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fixed bugs for UNIVERSAL and WILTON switch blocks
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2019-06-25 14:15:29 -06:00 |
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Baudouin Chauviere
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332ce17f03
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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tangxifan
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a88263a4c2
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update rr_block writer to include IPINs in XML files
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2019-06-25 11:17:22 -06:00 |
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tangxifan
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785b560bd5
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sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
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2019-06-24 22:46:56 -06:00 |
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tangxifan
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fd301eeb66
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many bug fixing and now start improving the routability of tileable rr_graph
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2019-06-24 17:33:29 -06:00 |
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tangxifan
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0d62661c71
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bug fixing and spot critical bugs in directlist parser
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2019-06-23 20:52:38 -06:00 |