Commit Graph

26 Commits

Author SHA1 Message Date
tangxifan 5cb3717433 add single mode test case to regression test. debugging now 2019-10-28 15:57:17 -06:00
Baudouin Chauviere 027272c976 Faster regression test 2019-10-05 12:10:55 -06:00
Baudouin Chauviere db059af8b8 Lighten the regression test 2019-10-03 13:33:28 -06:00
Baudouin Chauviere c7e1f7d90b Added explicit_verilog to regression test in a clean way 2019-10-03 10:17:04 -06:00
Baudouin Chauviere 33e50bbc8c fix 2019-10-01 16:54:16 -06:00
Baudouin Chauviere 7c3ab38410 Hot fix 2019-10-01 16:40:16 -06:00
AurelienUoU feddcbcb21 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-23 11:41:38 -06:00
tangxifan 5efea159c5 Simplify part of regression test to min_route_chan_width 2019-09-22 11:14:33 -06:00
AurelienUoU cc0bfdd548 Add testcase in regression test for architecture with 1 IO cell/IO block 2019-09-20 10:27:26 -06:00
tangxifan 4e7af5cdc5 update tileable_routing test 2019-09-18 15:59:32 -06:00
tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix 2019-09-18 15:04:51 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
tangxifan 5abbfd6a0f add tileable routing to regression test 2019-09-16 20:45:02 -06:00
tangxifan f04565386f refactored behavioral mux branch verilog generation 2019-08-27 18:39:25 -06:00
tangxifan de8a6bc833 update regression tests 2019-08-26 21:00:15 -06:00
Ganesh Gore 7a3ff94116 Added blif task in travis script 2019-08-25 01:28:21 -06:00
Ganesh Gore 937ebd1b85 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-08-25 00:53:18 -06:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
Ganesh Gore 89589ddc1c Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-22 18:46:51 -06:00
Ganesh Gore 2f0acfad23 Updated travis to run regression task 2019-08-21 11:09:53 -06:00
tangxifan 59f1ac7310 add missing files and try to refactor submodule essential 2019-08-20 20:49:26 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 60e8d2b29f add missing files and try to refactor submodule essential 2019-08-20 16:13:08 -06:00
Ganesh Gore 8d0153d34e Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
Ganesh Gore 901932a4fc First draft: Working openfpga task flow 2019-08-16 09:44:50 -06:00
Ganesh Gore b82369dd96 Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00