tangxifan
|
ba4b7e3522
|
[core] developing tile module builder
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2023-07-16 15:18:09 -07:00 |
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tangxifan
|
c2ef5ca408
|
[core] developing top-left style tile info
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2023-07-14 22:48:44 -07:00 |
|
tangxifan
|
091ac88c7e
|
[lib] code format
|
2023-07-14 12:16:40 -07:00 |
|
tangxifan
|
3bc959dcec
|
[lib] create tile config lib and start integration to core
|
2023-07-14 12:13:31 -07:00 |
|
tangxifan
|
c58035dbd4
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[core] start developing option --group_tile for build_fabric
|
2023-07-14 11:01:04 -07:00 |
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tangxifan
|
3de4d3fc09
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[core] add a new command 'write_fabric_key' and now writer supports module-level keys
|
2023-07-08 18:12:51 -07:00 |
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tangxifan
|
ddfb0c4afd
|
[core] now mock fpga top supports fpga core wrapper
|
2023-06-26 15:06:11 -07:00 |
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tangxifan
|
205881d0e7
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[core] fixed the bug when using fpga_core instead of fpga_top
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2023-06-25 18:03:15 -07:00 |
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tangxifan
|
150653287d
|
[core] supporting io naming for verilog testbench generators
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2023-06-25 15:29:27 -07:00 |
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tangxifan
|
8bd9ae02fd
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[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
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tangxifan
|
7961223eac
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[core] enabling io naming rules in fabric builder
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2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
61544af2b4
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[core] start adding new options
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2023-06-21 14:01:00 -07:00 |
|
tangxifan
|
299b42873d
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[core] fix no warning build
|
2023-06-19 13:01:43 -07:00 |
|
tangxifan
|
cef573529d
|
[core] now fpga verilog can output fpga core netlist
|
2023-06-18 21:17:50 -07:00 |
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tangxifan
|
c7ade72200
|
[core] code complete for the core wrapper creator. Start debugging
|
2023-06-18 19:17:42 -07:00 |
|
tangxifan
|
8bc70b590a
|
[core] developing fpga_core insertion
|
2023-06-17 23:42:45 -07:00 |
|
tangxifan
|
ee59bdb675
|
[core] code format
|
2023-06-07 18:55:34 -07:00 |
|
tangxifan
|
327f7f4dab
|
[core] now adapt to latest API of DeviceGrid
|
2023-06-07 18:54:48 -07:00 |
|
tangxifan
|
a9e5e1af89
|
[core] now fabric netlist include mock wrapper
|
2023-05-26 18:49:57 -07:00 |
|
tangxifan
|
45e25e4152
|
[core] hooking up API with command
|
2023-05-25 19:50:39 -07:00 |
|
tangxifan
|
ab263aa5b1
|
[core] code format
|
2023-05-25 15:02:03 -07:00 |
|
tangxifan
|
8d7429fc2b
|
[core] adding the new command 'write_mock_fpga_wrapper'
|
2023-05-25 12:58:12 -07:00 |
|
tangxifan
|
ea8ae29b53
|
[core] code format
|
2023-04-22 15:12:38 +08:00 |
|
tangxifan
|
297a23dee7
|
[core] fixed syntax errors
|
2023-04-22 15:09:39 +08:00 |
|
tangxifan
|
f70cc32824
|
[core] developing checkers for configuration protocol w.r.t. the programming clocks
|
2023-04-22 08:46:36 +08:00 |
|
tangxifan
|
50e201feeb
|
[core] now clock routing for programmable clock network works for 1 clock design
|
2023-03-07 13:13:25 -08:00 |
|
tangxifan
|
2ff3ad61ce
|
[core] format
|
2023-03-06 21:57:44 -08:00 |
|
tangxifan
|
45107bf14f
|
[core] debugging
|
2023-03-06 21:48:19 -08:00 |
|
tangxifan
|
6f2572324e
|
[core] developing route clock rr_graph command
|
2023-02-28 11:52:38 -08:00 |
|
tangxifan
|
b3dec93eb9
|
[core] code format
|
2023-02-27 15:12:59 -08:00 |
|
tangxifan
|
b6eace8fac
|
[core] now switch id is linked in clock network
|
2023-02-27 13:10:54 -08:00 |
|
tangxifan
|
009d711ba5
|
[core] code format
|
2023-02-26 22:23:41 -08:00 |
|
tangxifan
|
87a9146082
|
[core] adding rr spatial lookup for clock nodes only
|
2023-02-26 22:23:17 -08:00 |
|
tangxifan
|
780fc0f26d
|
[core] developing validators and annotate rr_segment for clock arch
|
2023-02-26 18:03:55 -08:00 |
|
tangxifan
|
7f07a9d031
|
[lib] add default seg/switch to clock arch. Fixed syntax
|
2023-02-24 19:15:39 -08:00 |
|
tangxifan
|
ee0459d729
|
[core] developing append_clock_rr_graph function
|
2023-02-24 17:58:37 -08:00 |
|
tangxifan
|
aa55c692d7
|
[core] starting developing core function for clock rr_graph build-up
|
2023-02-23 18:04:07 -08:00 |
|
tangxifan
|
786b458a27
|
[core] adding new command 'append_clock_rr_graph'
|
2023-02-23 13:30:18 -08:00 |
|
tangxifan
|
b78ca69fe5
|
[core] enable clock arch link
|
2023-02-22 22:29:16 -08:00 |
|
tangxifan
|
e1dab3d227
|
[code] format
|
2023-02-22 22:01:24 -08:00 |
|
tangxifan
|
e175472a07
|
[core] adding new commands
|
2023-02-22 21:58:25 -08:00 |
|
tangxifan
|
f00acf1e62
|
[code] fixed all the compiler warnings under openfpga/src
|
2023-01-31 12:51:52 -08:00 |
|
tangxifan
|
c55d54d325
|
[code] format
|
2023-01-11 17:19:04 -08:00 |
|
tangxifan
|
c00c43cbd4
|
[core] fixed a few bugs
|
2023-01-11 16:39:25 -08:00 |
|
tangxifan
|
9bbb09ef0f
|
[core] adding a new command 'exec_external' to run system call
|
2023-01-11 16:31:26 -08:00 |
|
tangxifan
|
b569d6b603
|
[core] format
|
2023-01-07 11:40:17 -08:00 |
|
tangxifan
|
c7a4d25e35
|
[core] now all the commands can be optionally hidden
|
2023-01-07 11:36:10 -08:00 |
|
tangxifan
|
4385b364af
|
[code] now setup command can be hidden optionally
|
2023-01-07 11:18:43 -08:00 |
|
tangxifan
|
52e803804d
|
[core] add missing file
|
2023-01-06 22:37:55 -08:00 |
|
tangxifan
|
2fc047daff
|
[core] format
|
2023-01-06 21:11:12 -08:00 |