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[core] code format

This commit is contained in:
tangxifan 2023-05-25 15:02:03 -07:00
parent d7837b8eeb
commit ab263aa5b1
2 changed files with 7 additions and 7 deletions
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8
openfpga/src/base/openfpga_verilog_command_template.h
View File

@ -305,10 +305,12 @@ ShellCommandId add_write_mock_fpga_wrapper_command_template(
/* add command to the shell */
ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate a wrapper of a mock fpga fabric mapped with applications", hidden);
shell_cmd,
"generate a wrapper of a mock fpga fabric mapped with applications",
hidden);
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(
shell_cmd_id, write_mock_fpga_wrapper_template<T>);
shell.set_command_execute_function(shell_cmd_id,
write_mock_fpga_wrapper_template<T>);
/* add command dependency to the shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds);

6
openfpga/src/base/openfpga_verilog_template.h
View File

@ -212,9 +212,8 @@ int write_preconfigured_fabric_wrapper_template(
*FPGA-Verilog
*******************************************************************/
template <class T>
int write_mock_fpga_wrapper_template(
const T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) {
int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_bgf = cmd.option("bus_group_file");
@ -261,7 +260,6 @@ int write_mock_fpga_wrapper_template(
openfpga_ctx.arch().config_protocol, options);
}
/********************************************************************
* A wrapper function to call the preconfigured testbench generator of
*FPGA-Verilog