diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h
index e61938008..c1b7e6c64 100644
--- a/openfpga/src/base/openfpga_verilog_command_template.h
+++ b/openfpga/src/base/openfpga_verilog_command_template.h
@@ -305,10 +305,12 @@ ShellCommandId add_write_mock_fpga_wrapper_command_template(
 
   /* add command to the shell */
   ShellCommandId shell_cmd_id = shell.add_command(
-    shell_cmd, "generate a wrapper of a mock fpga fabric mapped with applications", hidden);
+    shell_cmd,
+    "generate a wrapper of a mock fpga fabric mapped with applications",
+    hidden);
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(
-    shell_cmd_id, write_mock_fpga_wrapper_template<T>);
+  shell.set_command_execute_function(shell_cmd_id,
+                                     write_mock_fpga_wrapper_template<T>);
 
   /* add command dependency to the shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 107952c5d..cc88dcf3f 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -212,9 +212,8 @@ int write_preconfigured_fabric_wrapper_template(
  *FPGA-Verilog
  *******************************************************************/
 template <class T>
-int write_mock_fpga_wrapper_template(
-  const T& openfpga_ctx, const Command& cmd,
-  const CommandContext& cmd_context) {
+int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd,
+                                     const CommandContext& cmd_context) {
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
   CommandOptionId opt_bgf = cmd.option("bus_group_file");
@@ -261,7 +260,6 @@ int write_mock_fpga_wrapper_template(
     openfpga_ctx.arch().config_protocol, options);
 }
 
-
 /********************************************************************
  * A wrapper function to call the preconfigured testbench generator of
  *FPGA-Verilog