[core] adding the new command 'write_mock_fpga_wrapper'
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tangxifan
parent
4a90dd56b5
commit
8d7429fc2b
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@ -251,6 +251,71 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template(
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return shell_cmd_id;
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}
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/********************************************************************
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* - add a command to shell environment: write mock fpga wrapper
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* - add associated options
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* - add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_mock_fpga_wrapper_command_template(
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openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
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Command shell_cmd("write_mock_fpga_wrapper");
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/* add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "specify the output directory for hdl netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt =
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shell_cmd.add_option("pin_constraints_file", false,
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"specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* add an option '--bus_group_file in short '-bgf' */
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CommandOptionId bgf_opt = shell_cmd.add_option(
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"bus_group_file", false, "specify the file path to the group pins to bus");
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shell_cmd.set_option_short_name(bgf_opt, "bgf");
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shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING);
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false,
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"use explicit port mapping in verilog netlists");
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/* Add an option '--default_net_type' */
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CommandOptionId default_net_type_opt = shell_cmd.add_option(
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"default_net_type", false,
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"Set the default net type for Verilog netlists. Default value is 'none'");
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shell_cmd.set_option_require_value(default_net_type_opt,
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openfpga::OPT_STRING);
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false,
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"use explicit port mapping in verilog netlists");
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/* Add an option '--no_time_stamp' */
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shell_cmd.add_option("no_time_stamp", false,
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"Do not print a time stamp in the output files");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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/* add command to the shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd, "generate a wrapper of a mock fpga fabric mapped with applications", hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(
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shell_cmd_id, write_mock_fpga_wrapper_template<T>);
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/* add command dependency to the shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: write preconfigured testbench
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* - Add associated options
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@ -435,6 +500,17 @@ void add_verilog_command_templates(openfpga::Shell<T>& shell,
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shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds,
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hidden);
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/********************************
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* Command 'write_mock_fpga_wrapper'
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*/
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/* The command 'write_mock_fpga_wrapper' should NOT be executed
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* before 'build_fabric' */
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std::vector<ShellCommandId> write_mock_fpga_wrapper_dependent_cmds;
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write_mock_fpga_wrapper_dependent_cmds.push_back(build_fabric_cmd_id);
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add_write_mock_fpga_wrapper_command_template<T>(
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shell, openfpga_verilog_cmd_class, write_mock_fpga_wrapper_dependent_cmds,
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hidden);
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/********************************
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* Command 'write_preconfigured_testbench'
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*/
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@ -207,6 +207,61 @@ int write_preconfigured_fabric_wrapper_template(
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openfpga_ctx.arch().config_protocol, options);
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}
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/********************************************************************
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* A wrapper function to call the mock fpga wrapper generator of
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*FPGA-Verilog
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*******************************************************************/
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template <class T>
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int write_mock_fpga_wrapper_template(
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const T& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_bgf = cmd.option("bus_group_file");
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CommandOptionId opt_explicit_port_mapping =
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cmd.option("explicit_port_mapping");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the
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* FPGA-Verilog Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_explicit_port_mapping(
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cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(
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cmd_context.option_value(cmd, opt_default_net_type));
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}
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/* If pin constraints are enabled by command options, read the file */
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PinConstraints pin_constraints;
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if (true == cmd_context.option_enable(cmd, opt_pcf)) {
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pin_constraints =
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read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
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}
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/* If bug group file are enabled by command options, read the file */
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BusGroup bus_group;
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if (true == cmd_context.option_enable(cmd, opt_bgf)) {
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bus_group =
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read_xml_bus_group(cmd_context.option_value(cmd, opt_bgf).c_str());
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}
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return fpga_verilog_preconfigured_fabric_wrapper(
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openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
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g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
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openfpga_ctx.io_location_map(), openfpga_ctx.fabric_global_port_info(),
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openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol, options);
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}
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/********************************************************************
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* A wrapper function to call the preconfigured testbench generator of
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*FPGA-Verilog
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