diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h
index 266afc6d8..e61938008 100644
--- a/openfpga/src/base/openfpga_verilog_command_template.h
+++ b/openfpga/src/base/openfpga_verilog_command_template.h
@@ -251,6 +251,71 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template(
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - add a command to shell environment: write mock fpga wrapper
+ * - add associated options
+ * - add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_write_mock_fpga_wrapper_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("write_mock_fpga_wrapper");
+
+  /* add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option(
+    "file", true, "specify the output directory for hdl netlists");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* add an option '--pin_constraints_file in short '-pcf' */
+  CommandOptionId pcf_opt =
+    shell_cmd.add_option("pin_constraints_file", false,
+                         "specify the file path to the pin constraints");
+  shell_cmd.set_option_short_name(pcf_opt, "pcf");
+  shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
+
+  /* add an option '--bus_group_file in short '-bgf' */
+  CommandOptionId bgf_opt = shell_cmd.add_option(
+    "bus_group_file", false, "specify the file path to the group pins to bus");
+  shell_cmd.set_option_short_name(bgf_opt, "bgf");
+  shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING);
+
+  /* add an option '--explicit_port_mapping' */
+  shell_cmd.add_option("explicit_port_mapping", false,
+                       "use explicit port mapping in verilog netlists");
+
+  /* Add an option '--default_net_type' */
+  CommandOptionId default_net_type_opt = shell_cmd.add_option(
+    "default_net_type", false,
+    "Set the default net type for Verilog netlists. Default value is 'none'");
+  shell_cmd.set_option_require_value(default_net_type_opt,
+                                     openfpga::OPT_STRING);
+
+  /* add an option '--explicit_port_mapping' */
+  shell_cmd.add_option("explicit_port_mapping", false,
+                       "use explicit port mapping in verilog netlists");
+
+  /* Add an option '--no_time_stamp' */
+  shell_cmd.add_option("no_time_stamp", false,
+                       "Do not print a time stamp in the output files");
+
+  /* add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "enable verbose output");
+
+  /* add command to the shell */
+  ShellCommandId shell_cmd_id = shell.add_command(
+    shell_cmd, "generate a wrapper of a mock fpga fabric mapped with applications", hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(
+    shell_cmd_id, write_mock_fpga_wrapper_template<T>);
+
+  /* add command dependency to the shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 /********************************************************************
  * - Add a command to Shell environment: write preconfigured testbench
  * - Add associated options
@@ -435,6 +500,17 @@ void add_verilog_command_templates(openfpga::Shell<T>& shell,
     shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds,
     hidden);
 
+  /********************************
+   * Command 'write_mock_fpga_wrapper'
+   */
+  /* The command 'write_mock_fpga_wrapper' should NOT be executed
+   * before 'build_fabric' */
+  std::vector<ShellCommandId> write_mock_fpga_wrapper_dependent_cmds;
+  write_mock_fpga_wrapper_dependent_cmds.push_back(build_fabric_cmd_id);
+  add_write_mock_fpga_wrapper_command_template<T>(
+    shell, openfpga_verilog_cmd_class, write_mock_fpga_wrapper_dependent_cmds,
+    hidden);
+
   /********************************
    * Command 'write_preconfigured_testbench'
    */
diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 3f042ddcc..107952c5d 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -207,6 +207,61 @@ int write_preconfigured_fabric_wrapper_template(
     openfpga_ctx.arch().config_protocol, options);
 }
 
+/********************************************************************
+ * A wrapper function to call the mock fpga wrapper generator of
+ *FPGA-Verilog
+ *******************************************************************/
+template <class T>
+int write_mock_fpga_wrapper_template(
+  const T& openfpga_ctx, const Command& cmd,
+  const CommandContext& cmd_context) {
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
+  CommandOptionId opt_bgf = cmd.option("bus_group_file");
+  CommandOptionId opt_explicit_port_mapping =
+    cmd.option("explicit_port_mapping");
+  CommandOptionId opt_default_net_type = cmd.option("default_net_type");
+  CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* This is an intermediate data structure which is designed to modularize the
+   * FPGA-Verilog Keep it independent from any other outside data structures
+   */
+  VerilogTestbenchOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_explicit_port_mapping(
+    cmd_context.option_enable(cmd, opt_explicit_port_mapping));
+  options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
+  options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
+
+  if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
+    options.set_default_net_type(
+      cmd_context.option_value(cmd, opt_default_net_type));
+  }
+
+  /* If pin constraints are enabled by command options, read the file */
+  PinConstraints pin_constraints;
+  if (true == cmd_context.option_enable(cmd, opt_pcf)) {
+    pin_constraints =
+      read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
+  }
+
+  /* If bug group file are enabled by command options, read the file */
+  BusGroup bus_group;
+  if (true == cmd_context.option_enable(cmd, opt_bgf)) {
+    bus_group =
+      read_xml_bus_group(cmd_context.option_value(cmd, opt_bgf).c_str());
+  }
+
+  return fpga_verilog_preconfigured_fabric_wrapper(
+    openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
+    g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
+    openfpga_ctx.io_location_map(), openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
+    openfpga_ctx.arch().config_protocol, options);
+}
+
+
 /********************************************************************
  * A wrapper function to call the preconfigured testbench generator of
  *FPGA-Verilog