tangxifan
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1225679aac
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[core] code format
|
2024-08-06 17:35:44 -07:00 |
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tangxifan
|
0dba4082d1
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[core] syntax
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2024-08-06 17:20:34 -07:00 |
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tangxifan
|
ac2337d24b
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[core] rework the option 'constant_undriven_inputs'
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2024-08-06 16:50:49 -07:00 |
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tangxifan
|
703cbddc9e
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[core] code format
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2024-07-06 12:14:57 -07:00 |
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tangxifan
|
1f8c2436ef
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[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
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2024-07-04 20:46:38 -07:00 |
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tangxifan
|
72ee39f178
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[core] add new command line option 'constant_undriven_inputs'
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2024-07-04 20:39:02 -07:00 |
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tangxifan
|
00de794967
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[core] code format
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2024-03-29 10:58:48 -07:00 |
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tangxifan
|
981828c39c
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[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
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2024-03-29 10:57:45 -07:00 |
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tangxifan
|
bacd845139
|
[core] code format
|
2023-12-08 13:41:41 -08:00 |
|
tangxifan
|
5e181cbe72
|
[core] add a new option for simulator type to verilog full testbench generator
|
2023-12-08 13:07:25 -08:00 |
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tangxifan
|
649d44b2d8
|
[core] code format
|
2023-11-02 16:33:55 -07:00 |
|
tangxifan
|
36fa020c15
|
[core] syntax
|
2023-11-02 16:33:19 -07:00 |
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tangxifan
|
75e9e98e5d
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[core] add two new commands to output testbench parts
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2023-11-02 16:06:48 -07:00 |
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tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
|
tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
|
4ccb4737be
|
[core] code format
|
2023-09-17 17:33:10 -07:00 |
|
tangxifan
|
f79da76656
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[core] supporting renaming on all the verilog modules
|
2023-09-17 17:29:11 -07:00 |
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tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
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tangxifan
|
ddfb0c4afd
|
[core] now mock fpga top supports fpga core wrapper
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2023-06-26 15:06:11 -07:00 |
|
tangxifan
|
205881d0e7
|
[core] fixed the bug when using fpga_core instead of fpga_top
|
2023-06-25 18:03:15 -07:00 |
|
tangxifan
|
150653287d
|
[core] supporting io naming for verilog testbench generators
|
2023-06-25 15:29:27 -07:00 |
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tangxifan
|
a9e5e1af89
|
[core] now fabric netlist include mock wrapper
|
2023-05-26 18:49:57 -07:00 |
|
tangxifan
|
45e25e4152
|
[core] hooking up API with command
|
2023-05-25 19:50:39 -07:00 |
|
tangxifan
|
ab263aa5b1
|
[core] code format
|
2023-05-25 15:02:03 -07:00 |
|
tangxifan
|
8d7429fc2b
|
[core] adding the new command 'write_mock_fpga_wrapper'
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2023-05-25 12:58:12 -07:00 |
|
tangxifan
|
401b640852
|
[core] format
|
2023-01-06 17:50:47 -08:00 |
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tangxifan
|
12134f4106
|
[core] now openfpga verilog commands follow templates
|
2023-01-06 17:48:00 -08:00 |