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OpenFPGA
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7367 Commits

Author SHA1 Message Date
tangxifan 572860714c
Merge pull request #1682 from lnis-uofu/dependabot/submodules/yosys-5579685 
Bump yosys from `c71262f` to `5579685`
 2024-05-28 15:36:40 -07:00
dependabot[bot] 0a922b6504
Bump yosys from `c71262f` to `5579685` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `c71262f` to `5579685`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](c71262f66b...5579685673)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-05-27 06:09:54 +00:00
tangxifan 2196fc4697
Merge pull request #1681 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2024-05-23 11:42:07 -07:00
github-actions[bot] 043c9c4c20 Updated Patch Count 2024-05-23 18:41:16 +00:00
tangxifan f308378a25
Merge pull request #1680 from lnis-uofu/dependabot/submodules/yosys-c71262f 
Bump yosys from `7045cf5` to `c71262f`
 2024-05-23 11:40:44 -07:00
dependabot[bot] 2593cb2e3c
--- 
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-05-22 06:34:22 +00:00
tangxifan 286eacd601
Merge pull request #1679 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2024-05-21 14:16:05 -07:00
github-actions[bot] eb150154e8 Updated Patch Count 2024-05-21 21:06:55 +00:00
tangxifan 9fa3b53aab
Merge pull request #1678 from lnis-uofu/xt_ecb 
Support Enhanced Connection Block
 2024-05-21 14:04:12 -07:00
tangxifan d31e3bb8bf Merge branch 'xt_ecb' of github.com:lnis-uofu/OpenFPGA into xt_ecb 2024-05-21 11:14:27 -07:00
tangxifan 391b768b3a [doc] syntax 2024-05-21 11:14:12 -07:00
tangxifan d5ffb44417
Merge branch 'master' into xt_ecb 2024-05-21 11:06:28 -07:00
tangxifan 2155d42dc0
Merge pull request #1677 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-ec85a46 
Bump vtr-verilog-to-routing from `48c0303` to `ec85a46`
 2024-05-21 11:05:54 -07:00
tangxifan 4c6b923b74 [doc] add a figure about ecb 2024-05-21 11:03:58 -07:00
tangxifan 5775187072 [doc] enhance connection block details and restrictions 2024-05-21 10:55:13 -07:00
dependabot[bot] 8069579095
--- 
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-05-21 06:27:54 +00:00
tangxifan 3c49af6a08 [test] code format 2024-05-20 21:28:46 -07:00
tangxifan f25081eb31 [test] add a new test to validate ecb when tile modules are used 2024-05-20 21:10:49 -07:00
tangxifan 852b01aaff [test] rework 2024-05-20 17:20:04 -07:00
tangxifan d3d29a507f [lib] update vtr 2024-05-20 17:17:10 -07:00
tangxifan 5fbf6c5621
Merge pull request #1676 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2024-05-20 17:15:01 -07:00
github-actions[bot] 84a85fa81b Updated Patch Count 2024-05-21 00:02:42 +00:00
tangxifan a9a5fbee34 [test] add fully connected feedback connections to directlist 2024-05-20 17:02:20 -07:00
tangxifan 52ae484a7c [core] fixed a bug on messed up wire connections for OPINs 2024-05-20 13:50:31 -07:00
tangxifan 807c37d3ff [test] fixed some bugs 2024-05-20 13:47:22 -07:00
tangxifan 6146d0be9f [arch] Move clb I to right side as left side is not supported yet 2024-05-20 13:43:04 -07:00
tangxifan ca6e2f9831 [core] code format 2024-05-20 13:41:35 -07:00
tangxifan 8c3da74835 [lib] update vtr 2024-05-20 13:32:39 -07:00
tangxifan 4a791249bf [core] fixed a bug on requirement wire model for direction connection which is part of a cb 2024-05-20 12:52:07 -07:00
tangxifan b15e169490 [core] fixed a bug where wire model is expected on direct connections 2024-05-20 12:45:49 -07:00
tangxifan 65dd342c60 [arch] typo 2024-05-20 12:11:22 -07:00
tangxifan 653521755b [test] add new testcase for ecb to basic regtest 2024-05-20 12:09:12 -07:00
tangxifan bdc13e491e [arch] adding openfpga arch for ecb 2024-05-20 12:04:52 -07:00
tangxifan c795dd2f1a [arch] adding a new arch where feedback loops are modelled by direct connections 2024-05-20 12:00:39 -07:00
tangxifan 1b8b5bc7ba
Merge pull request #1675 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-48c0303 
Bump vtr-verilog-to-routing from `26bac8c` to `48c0303`
 2024-05-20 11:36:56 -07:00
tangxifan 65a8db4f38 [arch] replace out-of-date keywords 2024-05-20 11:18:46 -07:00
tangxifan 9d87e99539 [lib] typo on keywords in XML parser 2024-05-20 11:15:43 -07:00
dependabot[bot] 03e1511fa6
Bump vtr-verilog-to-routing from `26bac8c` to `48c0303` 
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `26bac8c` to `48c0303`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](26bac8cbac...48c03037f3)

---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-05-20 06:49:14 +00:00
tangxifan b554a3d855 [core] code format 2024-05-19 17:24:38 -07:00
tangxifan 1a05c30b72 [lib] update vtr to latest 2024-05-19 17:24:08 -07:00
tangxifan 56aaa6a1f4 [core] sytax 2024-05-19 17:23:48 -07:00
tangxifan 065d77c679 [core] supporting opin connection to cb in tiles 2024-05-19 17:04:24 -07:00
tangxifan 9079056871 [core] now connect OPIN to CB in top-level module 2024-05-19 14:27:36 -07:00
tangxifan 5e0d208cc4 [core] update vtr 2024-05-19 14:20:56 -07:00
tangxifan 918bf79ca3 [core] update vtr and developing caches for OPIN lists just for connection blocks 2024-05-19 14:10:00 -07:00
tangxifan 772da3006b [core] code format 2024-05-18 22:19:17 -07:00
tangxifan 304f34525e [core] syntax 2024-05-18 22:17:52 -07:00
tangxifan b533ea4060 [core] now cb module include OPIN nodes 2024-05-18 22:00:02 -07:00
tangxifan 926b9e9739 [core] code format 2024-05-18 12:33:19 -07:00
tangxifan 3b93bea3d1 [core] syntax 2024-05-18 12:29:38 -07:00