tangxifan
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2de4a460a8
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[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
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2021-09-24 15:15:32 -07:00 |
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tangxifan
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74ffc8578f
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[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
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2021-09-24 15:05:25 -07:00 |
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tangxifan
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be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
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18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
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7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
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8c281a22b0
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[Engine] Add check codes to validate circuit models for BL/WL protocols
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2021-09-23 14:39:16 -07:00 |
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tangxifan
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6645b70ae3
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[Engine] Upgrade parser to support BL/WL protocols
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2021-09-23 14:25:25 -07:00 |
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tangxifan
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d4e3445153
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[Engine] update internal data structure for new syntax in configuration protocol
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2021-09-22 17:32:45 -07:00 |
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tangxifan
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1ca1b0f3e9
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[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
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2021-09-22 15:58:05 -07:00 |
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tangxifan
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655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
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a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
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53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
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3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
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212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
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182e9a7baf
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Merge pull request #15 from RapidSilicon/phy_mem_bank
Support multi-region for QL memory bank configuration protocol
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2021-09-22 14:37:17 -07:00 |
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tangxifan
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b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
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efed268585
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[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
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2021-09-22 11:30:08 -07:00 |
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tangxifan
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abfa380333
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[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
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337ed33b68
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[Test] Added a sample fabric key for 2-region QL memory bank
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2021-09-22 11:25:16 -07:00 |
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tangxifan
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962acda810
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[Engine] Bug fix in fabric key generation when computing configurable children
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2021-09-22 11:09:46 -07:00 |
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tangxifan
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ad432e4d95
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[Engine] Bug fix in finding the start index of BL/WL for each column/row;
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2021-09-22 10:20:40 -07:00 |
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tangxifan
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7db7e2d8f6
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[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
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2021-09-22 10:05:27 -07:00 |
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tangxifan
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d0fe12fadd
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[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
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51fc222d61
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[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
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303baa4fc9
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Merge pull request #14 from RapidSilicon/phy_mem_bank
Support fabric key for QL memory bank
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2021-09-21 20:31:07 -07:00 |
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tangxifan
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1603c9b404
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Merge pull request #374 from foggy-slt/patch-1
Update fpgaflow_default_tool_path.conf
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2021-09-21 19:02:29 -07:00 |
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tangxifan
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10774dc15c
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[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
|
e09ab2298e
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[Engine] Bug fix in fabric key parser on identifying invalid coordinate
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2021-09-21 16:45:14 -07:00 |
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tangxifan
|
ab42239b94
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[Test] Bug fix in the fabric key
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2021-09-21 16:44:58 -07:00 |
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tangxifan
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f57aceff87
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[Test] Deploy the load external key test case for ql memory bank to basic regression tests
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2021-09-21 16:25:14 -07:00 |
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tangxifan
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aad47ffbc6
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[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
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2021-09-21 16:22:50 -07:00 |
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tangxifan
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1412121541
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[Test] Added a new test to validate the fabric key parser for QL memory bank
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2021-09-21 16:20:24 -07:00 |
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tangxifan
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cd0d8b86fa
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[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
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2021-09-21 15:55:34 -07:00 |
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tangxifan
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b0a471bdc9
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[Engine] Bug fix in outputting fabric key with coordinates
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2021-09-21 15:55:11 -07:00 |
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tangxifan
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7327850cf3
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[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
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2021-09-21 15:43:54 -07:00 |
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tangxifan
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dc2d1d1c3c
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[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
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2021-09-21 15:42:20 -07:00 |
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tangxifan
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7688c0570f
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[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
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2021-09-21 15:08:08 -07:00 |
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tangxifan
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8a3ce62d70
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Merge pull request #10 from RapidSilicon/phy_mem_bank
Support WLR signal in physical friendly memory bank
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2021-09-20 21:33:21 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
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3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
|
d36d1ebee2
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[HDL] Temporarily disable WLR func in primitive HDL modeling
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2021-09-20 17:07:51 -07:00 |
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tangxifan
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c84c0d4a3f
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[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
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2021-09-20 17:07:26 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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0450d57d82
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[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
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2021-09-20 16:05:01 -07:00 |
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tangxifan
|
3f6ac41868
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[Test] Deploy the WLR test to the basic regression tests
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2021-09-20 11:21:58 -07:00 |
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tangxifan
|
60fc3ab36c
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[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
|
5c1c428ea5
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[HDL] Updated cell library with the SRAM cell with Read Enable signal
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2021-09-20 11:13:36 -07:00 |
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tangxifan
|
cd2978a434
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[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
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2021-09-20 11:13:02 -07:00 |
slt
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b867db815f
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Update fpgaflow_default_tool_path.conf
Update regex for VPR
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2021-09-17 14:02:26 +08:00 |
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tangxifan
|
6d151527ca
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Merge pull request #8 from RapidSilicon/phy_mem_bank
Reduce Unique BL/WLs for Top-level Module in Physical Design Friendly Memory Bank
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2021-09-15 16:07:22 -07:00 |