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4,307 Commits 70 Branches 8 Tags 105 MiB
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4307 Commits

Author SHA1 Message Date
tangxifan cf96d9ff01 [Engine] Add programming shift register clock to internal global port data structure 2021-10-01 11:05:31 -07:00
tangxifan dda147e234 [Flow] Add an example simulation setting file for defining programming shift register clocks 2021-10-01 11:04:23 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan fa57117f50 [Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers 2021-10-01 10:19:51 -07:00
tangxifan 96828e456a [FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong 2021-09-30 22:07:46 -07:00
tangxifan 4bdff1554d [Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken 2021-09-30 21:20:56 -07:00
tangxifan 33972fc0ec [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
tangxifan 4526133089 [FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers 2021-09-30 17:01:02 -07:00
tangxifan 43c569b612 [FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object 2021-09-30 14:47:21 -07:00
tangxifan 4d8019b7c1 [FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank 2021-09-29 22:32:45 -07:00
tangxifan 2d4c200d58 [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
tangxifan f456c7e236 [Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules 2021-09-29 20:34:25 -07:00
tangxifan b87b7a99c5 [Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators 2021-09-29 20:21:46 -07:00
tangxifan 8f0ae937bc [Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank 2021-09-29 16:57:49 -07:00
tangxifan 41cc375746 [Arch] define default CCFF model in ql bank example architecture that uses shift registers 2021-09-29 16:34:40 -07:00
tangxifan 4926c323e7 [Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML 2021-09-29 16:32:29 -07:00
tangxifan 89a97d83bd [Test] Added a new test case for the shift register banks in QuickLogic memory banks 2021-09-29 16:28:06 -07:00
tangxifan ac6268d9ae [Engine] Bug fix on compilation errors 2021-09-29 16:24:36 -07:00
tangxifan c5ae93f177 [Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank 2021-09-29 16:17:40 -07:00
tangxifan 5da8f1db73 [Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules 2021-09-28 23:27:47 -07:00
tangxifan 7723e00e6c [Engine] Adding the function that builds a shift register module for BL/WLs 2021-09-28 22:49:24 -07:00
tangxifan 834bdd2b07 [Engine] Updating fabric generator to support BL/WL shift registers. Still WIP 2021-09-28 17:29:03 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 0a2979d616 [Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols 2021-09-28 14:20:35 -07:00
tangxifan 4968f0d11f Merge branch 'master' into qlbank_sr 2021-09-28 14:20:30 -07:00
tangxifan 7633951263
Merge pull request #19 from RapidSilicon/phy_mem_bank 
Patch QuickLogic Memory Bank with Flatten BL/WL Protocol and WLR signals
 2021-09-28 13:26:57 -07:00
tangxifan 80232fc459 [Arch] Add a new example architecture for QL memory bank using WLR in shift registers 2021-09-28 12:36:36 -07:00
tangxifan 4c04c0fbd7 [Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models 2021-09-28 12:35:42 -07:00
tangxifan 2ce2fb269a [HDL] Added a different FF model which is designed to drive WLW only 2021-09-28 12:35:13 -07:00
tangxifan 6469ee3048 [HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs 2021-09-28 12:21:54 -07:00
tangxifan 0d72e115ac [Engine] Bug fix for the undriven WLR nets in top-level modules 2021-09-28 11:53:38 -07:00
tangxifan 4400dae108 [Test] Bug fix in the wrong arch name 2021-09-28 11:40:25 -07:00
tangxifan 4aed045cdd [Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs 2021-09-28 11:34:20 -07:00
tangxifan 811c898173 [Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests 2021-09-28 11:29:45 -07:00
tangxifan dae3554fd4 [Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals 2021-09-28 11:27:49 -07:00
tangxifan 05c6f1889e
Merge pull request #17 from RapidSilicon/phy_mem_bank 
Support flatten BL/WL protocol for QuickLogic memory bank
 2021-09-27 11:57:00 -07:00
tangxifan b0a97a7052 [Doc] Update doc about WLR usage for QL memory bank 2021-09-27 10:24:04 -07:00
tangxifan f9bceff33a [Doc] Update documentation for the flatten BL/WL protocols 2021-09-25 20:44:45 -07:00
tangxifan 33e9b27cb8 [Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs 2021-09-25 20:22:27 -07:00
tangxifan 29c351f5a4 [Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator 2021-09-25 19:34:21 -07:00
tangxifan e06ac11630 [Engine] Bug fix 2021-09-25 19:21:16 -07:00
tangxifan 3cf31f1565 [Engine] Fixed bugs 2021-09-25 18:22:55 -07:00
tangxifan a56d1f4fdb [FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs 2021-09-25 17:49:15 -07:00
tangxifan 386812777c [FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs 2021-09-25 12:49:32 -07:00
tangxifan 1a2a2a6e63 [FPGA-Bitstream] Relax fabric bitstream address check 2021-09-25 12:03:33 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan a49e3fe57a [FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank 2021-09-24 16:30:18 -07:00
tangxifan 025ee67bc7 [Engine] Clear up compiler warning in tileable rr_graph builder 2021-09-24 15:20:43 -07:00
tangxifan 5f7617b682 [Engine] Clear up compiler warnings in circuit library 2021-09-24 15:18:50 -07:00
tangxifan f735c10b84 [Engine] Clear up compiler warnings 2021-09-24 15:18:31 -07:00