coolbreeze413
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31379062e3
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remove minor comments
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2021-11-18 18:40:15 +05:30 |
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coolbreeze413
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91094305bd
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enable all tests except 15 and 19
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2021-11-17 20:56:12 +05:30 |
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coolbreeze413
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840fa399c6
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enable single counter test (fails, needs debug)
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2021-11-09 21:36:33 +05:30 |
tangxifan
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83d177b13b
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[Test] Deploy the newly added adder benchmarks to tests
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2021-06-30 15:14:24 -06:00 |
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tangxifan
|
e61857aa2b
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Merge branch 'master' into ganesh_dev
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2021-03-11 19:17:02 -07:00 |
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tangxifan
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366bec232c
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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
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2021-03-11 15:25:48 -07:00 |
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tangxifan
|
a6186db315
|
[Test] Update bitstream annotation with new syntax
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2021-03-10 20:45:17 -07:00 |
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tangxifan
|
7d07f5d8cb
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[Test] Update bitstream setting example with mode bit overwriting
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2021-03-10 15:34:53 -07:00 |
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tangxifan
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d21909ad6c
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[Test] Use custom rewriting script in lut_adder test
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2021-03-10 13:48:20 -07:00 |
Tarachand Pagarani
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db8ea86b2f
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update tests to use no_ff_map and remove tests that need async set/reset for now
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2021-03-10 10:04:45 -08:00 |
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Tarachand Pagarani
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608bd1f658
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comment out desings that utilize local async reset/preset
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2021-03-09 19:24:01 -08:00 |
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Tarachand Pagarani
|
7f4c20ff33
|
comment out desings that utilize local async reset/preset
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2021-03-09 10:37:06 -08:00 |
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Tarachand Pagarani
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c4b83aeaa9
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bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
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2021-03-09 00:46:40 -08:00 |
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tangxifan
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37aa42d305
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[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
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2021-03-08 21:38:51 -07:00 |
Lalit Sharma
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7945628307
|
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
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2021-03-07 22:25:01 -08:00 |
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Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
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Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
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817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
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Lalit Sharma
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ea4aee8cb2
|
For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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tangxifan
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0d82e4939c
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[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
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2021-02-26 09:35:40 -07:00 |
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tangxifan
|
870d3a0e27
|
Merge branch 'master' into dev
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2021-02-26 09:28:42 -07:00 |
|
Lalit Sharma
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1082d3c677
|
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
|
Lalit Sharma
|
1e48d4f6dc
|
Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
|
tangxifan
|
a62786986b
|
[Test] Turn off verification in adder lut test temporarily
|
2021-02-23 19:03:25 -07:00 |
|
tangxifan
|
53df7f69e7
|
[Test] Bug fix in the test case using lut adder
|
2021-02-23 16:59:46 -07:00 |
|
tangxifan
|
db71cc8a16
|
[Test] Add LUT adder test using quicklogic synthesis script
|
2021-02-23 16:50:58 -07:00 |
|
tangxifan
|
19f6b221b1
|
[Test] Rework comments on runtime
|
2021-02-22 15:25:57 -07:00 |
|
tangxifan
|
4803b0ce42
|
[Test] Add test case for sdc controller
|
2021-02-22 15:02:14 -07:00 |
|
tangxifan
|
2e2b1cb6e7
|
[Test] Use hetergenenous FPGA architecture in quicklogic tests
|
2021-02-22 13:41:04 -07:00 |
|
tangxifan
|
bc30f62c5a
|
[Test] Add test for sdc controller
|
2021-02-22 12:41:53 -07:00 |
|
tangxifan
|
60dc194d8f
|
[Test] Bug fix in the 5clock test case
|
2021-02-22 11:46:23 -07:00 |
|
tangxifan
|
71e0026a50
|
[Test] Add new test for 5-clock counter to quicklogic tests
|
2021-02-22 11:32:17 -07:00 |
|
tangxifan
|
bc8aa0ebc6
|
[Test] Remove routing test from quicklogic's flow test
|
2021-02-22 10:22:47 -07:00 |
|
Lalit Sharma
|
576e6753f6
|
Removing 2 more tests which are variant of and design
|
2021-02-19 09:11:19 -08:00 |
|
Lalit Sharma
|
6de0954ca5
|
Uncommenting all benchmarks except 2 that requires multiple clocks
|
2021-02-19 08:40:26 -08:00 |
|
Lalit Sharma
|
69cdc11ea5
|
Uncommenting the tests that are running fine
|
2021-02-18 04:17:12 -08:00 |
|
Lalit Sharma
|
44a979288b
|
Adding quicklogic tests and updating the corresponding conf file to run them
|
2021-02-16 23:08:38 -08:00 |
|
Tarachand Pagarani
|
426b6449d8
|
change the test to turn off power analysis
|
2021-02-15 02:45:38 -08:00 |
|
Lalit Sharma
|
2484721a45
|
Updating write_verilog_testbench by removing option explicit_port_mapping
|
2020-12-22 22:17:50 -08:00 |
|
Lalit Sharma
|
3c9e4919b4
|
Updating variable name in ys to call BLIF output file.
|
2020-12-18 03:18:46 -08:00 |
|
Lalit Sharma
|
891e2f8aa3
|
Adding arch xml from SOFA repo. Also updating the script with its file location
|
2020-12-16 04:14:18 -08:00 |
|
Lalit Sharma
|
0ee3efb306
|
Adding a testcase to run yosys quicklogic flow
|
2020-12-10 02:41:43 -08:00 |