tangxifan
|
e683e00032
|
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
|
2021-02-10 14:50:11 -07:00 |
|
tangxifan
|
9b86f3bb85
|
Merge branch 'master' into dev
|
2021-02-09 22:40:45 -07:00 |
|
tangxifan
|
22e675148e
|
[HDL] Add HDL codes for a super LUT with embedded carry logic
|
2021-02-09 21:13:22 -07:00 |
|
tangxifan
|
b81b74aa7c
|
[Arch] Patch architecture to support superLUT-related XML syntax
|
2021-02-09 20:23:32 -07:00 |
|
tangxifan
|
7dcc14d73f
|
[Arch] Bug fix in the example arch with super LUT
|
2021-02-09 15:52:22 -07:00 |
|
tangxifan
|
3ae501a5ea
|
[Test] Update test case to use dedicated eblif file
|
2021-02-09 15:51:57 -07:00 |
|
tangxifan
|
1712ee4edb
|
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
|
2021-02-09 15:41:21 -07:00 |
|
tangxifan
|
2b51b36dd6
|
[Test] Now use the super LUT arch in the test case
|
2021-02-09 15:27:44 -07:00 |
|
tangxifan
|
56284059de
|
[Test] Add a test case for a super LUT
|
2021-02-09 15:25:32 -07:00 |
|
tangxifan
|
304b26c97f
|
[Arch] Add example architectures for superLUT circuit model
|
2021-02-09 15:11:12 -07:00 |
|
tangxifan
|
1ce94040da
|
Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
|
2021-02-08 12:43:57 -07:00 |
|
tangxifan
|
80a4872ba0
|
Merge pull request #222 from lnis-uofu/gg_cleanup
[Flow] ACE is optional during flow script, only runs when power estimation is on
|
2021-02-08 10:08:47 -07:00 |
Ganesh Gore
|
ede5f8ed58
|
[Flow] Support multi-user enviroment for running task
|
2021-02-07 22:11:04 -07:00 |
AurelienAlacchi
|
00fc3d7622
|
Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
|
2021-02-05 09:53:28 -07:00 |
|
ganeshgore
|
ee14c15e58
|
Merge pull request #212 from lnis-uofu/soft_adder_lut_support
Support overloading LUT bitstream from attributes in .eblif file format
|
2021-02-04 21:55:02 -07:00 |
|
tangxifan
|
8853370c60
|
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
|
2021-02-04 20:20:10 -07:00 |
|
tangxifan
|
dc09c47411
|
[Arch] Remove packable from architecture files and replace with disable_packing
|
2021-02-04 18:03:56 -07:00 |
|
tangxifan
|
224bf6c686
|
Merge branch 'master' into dev
|
2021-02-04 17:21:15 -07:00 |
|
tangxifan
|
66bc370c4d
|
[Arch] Use disable_packing in architecture library
|
2021-02-04 16:29:03 -07:00 |
|
tangxifan
|
a4c266d59a
|
[Arch] Add pack patterns for soft adders; Still fail in packing
|
2021-02-03 19:11:15 -07:00 |
|
Ganesh Gore
|
6cdc31f073
|
[Flow] ACE is optional duign flow script
|
2021-02-03 19:07:48 -07:00 |
|
tangxifan
|
cac1160bf7
|
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
|
2021-02-03 11:20:56 -07:00 |
|
Ganesh Gore
|
df4a397470
|
[Cleanup] Removed deadcode
|
2021-02-03 10:35:14 -07:00 |
|
tangxifan
|
4c825b27b3
|
[Benchmark] Change to use adder lut4 to be consistent with architecture
|
2021-02-03 09:37:48 -07:00 |
|
tangxifan
|
31441c0b64
|
[Test] Deploy adder_8 to soft adder test
|
2021-02-03 09:26:38 -07:00 |
|
tangxifan
|
05d63567d0
|
[Benchmark] Use latest adder eblif file
|
2021-02-03 09:21:38 -07:00 |
Lalit Sharma
|
ebe66dea35
|
Bumping up latest yosys changes related to adder tech mapping
|
2021-02-03 14:30:06 +05:30 |
|
tangxifan
|
2c06960e4f
|
[Benchmark] Add subckt definition to micro benchmark and2.eblif
|
2021-02-02 15:51:16 -07:00 |
|
tangxifan
|
021520783b
|
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
|
2021-02-02 15:49:43 -07:00 |
|
tangxifan
|
dc320182b0
|
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
|
2021-02-02 15:04:43 -07:00 |
|
tangxifan
|
8e36ed1ab6
|
[Test] Update task configuration to use and2 eblif
|
2021-02-02 15:01:15 -07:00 |
|
tangxifan
|
62803dc044
|
[Benchmark] Add eblif example for and2 benchmark
|
2021-02-02 14:59:31 -07:00 |
|
tangxifan
|
5e2847bc41
|
[Test] Update test case to use eblif file
|
2021-02-02 09:33:41 -07:00 |
|
tangxifan
|
39e6f62d91
|
[Benchmark] Use eblif in naming the adder_8 micro benchmark
|
2021-02-02 09:32:42 -07:00 |
|
tangxifan
|
d3397f6936
|
[Script] Remove activity from bitstream setting example script
|
2021-02-02 09:25:36 -07:00 |
|
tangxifan
|
9ff5e7926b
|
[Test] Update test case to use the adder benchmark
|
2021-02-02 09:24:39 -07:00 |
|
tangxifan
|
7f14dfbe87
|
[Script] Add example script to use bitstream setting
|
2021-02-02 09:18:08 -07:00 |
|
tangxifan
|
04594cb7ab
|
[Test] Adapt bitstream annotatin file to parser's requirement
|
2021-02-01 17:38:36 -07:00 |
|
tangxifan
|
280c9620aa
|
[Test] Add an example bitstream annotation file
|
2021-02-01 16:01:21 -07:00 |
|
tangxifan
|
a6354fab7c
|
[Arch] Decide to move external bitstream definition to a separated XML file
|
2021-02-01 15:57:44 -07:00 |
|
tangxifan
|
df88e2adc0
|
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
|
2021-02-01 14:26:11 -07:00 |
|
tangxifan
|
10302752a7
|
[Arch] Bug fix in architecture. Now soft adder modes are accepted
|
2021-02-01 13:43:39 -07:00 |
|
tangxifan
|
d8927e12e8
|
[Arch] Add soft adder operating mode to test architecture
|
2021-02-01 12:25:37 -07:00 |
|
tangxifan
|
7f0f7a1c70
|
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
|
2021-02-01 12:05:04 -07:00 |
|
tangxifan
|
b215b868c1
|
[HDL] Bug fix in HDL netlist due to port name mismatching
|
2021-02-01 11:35:25 -07:00 |
|
tangxifan
|
e4abe263c3
|
[Arch] Bug fix
|
2021-02-01 11:29:27 -07:00 |
|
tangxifan
|
fb05e1a938
|
[Arch] bug fix due to using openfpga cell library
|
2021-02-01 11:27:21 -07:00 |
|
tangxifan
|
940dce469a
|
[Test] Bug fix for test case configuration
|
2021-02-01 11:19:47 -07:00 |
|
tangxifan
|
a80acfb547
|
[Test] Add new test case to CI script
|
2021-02-01 11:16:12 -07:00 |
|
tangxifan
|
af630dab1e
|
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
|
2021-02-01 10:53:38 -07:00 |